6

Rev. C

01/24/05

IS62C1024AL

IS65C1024AL

-35 ns

-45 ns

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

Write Cycle Time

35

—

45

—

ns

CE1 to Write End

25

—

35

—

ns

CE2 to Write End

25

—

35

—

ns

Address Setup Time to Write End

25

—

35

—

ns

Address Hold from Write End

0

—

0

—

ns

Address Setup Time

0

—

0

—

ns

WE Pulse Width

25

—

35

—

ns

Data Setup to Write End

20

—

25

—

ns

Data Hold from Write End

0

—

0

—

ns

WE LOW to High-Z Output

—

10

—

15

ns

WE HIGH to Low-Z Output

3

—

5

—

ns

Notes:

1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.6 to 2.4V

and output loading specified in Figure 1a.

2. Tested with the load in Figure 1b. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.

3. The internal write time is defined by the overlap of

CE1 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to

initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the

rising or falling edge of the signal that terminates the Write.

4. Tested with

OE HIGH.

Notes:

1.

WE is HIGH for a Read Cycle.

2. The device is continuously selected.

3. Address is valid prior to or coincident with

CE1 LOW and CE2 HIGH transitions.

HIGH-Z

DATA VALID

ADDRESS

OE

CE1

CE2

DOUT