DM562AP
V.90 Integrated Data/ Fax/Voice/Speakerphone
Modem Device Single Chip with Memory Built in
18
Preliminary
Version: DM562AP-DS-P02
March 05, 2004
Bit 1: This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic 1.
Bit 2: This bit enables the Receiver Line Status
Interrupt when set to logic 1.
Bit 3: This bit enables the MODEM Status Interrupt
when set to logic 1.
Bit 4-7: Not used
Interrupt Identification Register (IIR): Address 2
eset State 01h, Read only
Bit7
Bit6 bit5 bit4
bit3
bit2
bit1
bit0
FIFO
Enable
000
D3:
INTD2
D2:
INTD1
D1:
INTD0
D0:
int
Pending
In order to provide minimum software overhead during
data transfers, the virtual UART prioritizes interrupts
into four levels as follows: Receiver Line Status
(priority 1), Receiver Data Available (priority 2),
Character Timeout Indication (priority 2, FIFO mode
only), Transmitter Holding Register Empty (priority 3),
and Modem Status (priority 4).
The IIR register gives prioritized information regarding
the status of interrupt conditions. When accessed, the
IIR indicates the highest priority interrupt that is
pending.
Bit 0: This bit can be used in either a prioritized
interrupt or polled environment to indicate
whether an interrupt is pending. When this bit is
a logic 0, an interrupt is pending, and the IIR
contents may be used as a pointer to the
appropriate interrupt service routine. When bit 0
is a logic 1, no interrupt is pending, and polling
(if used) continues.
Bit 1-2: These two bits of the IIR are used to identify
the highest priority interrupt pending, as
indicated in the table below.
Bit 3: In character mode, this bit is 0. In FIFO mode,
this bit is set, along with bit 2, when a timeout
interrupt is pending.
Bit 4-6: Not used
Bit 7: FIFO always enabled.
Interrupt Identification Register (IIR): Address 2 (continued)
D3 D2 D1 D0 Priority Level
Interrupt Type
Condition
Reset
0
0
01-
-
-
-
0
1
1
0
Highest
Receiver Line
Status
Overrun Error, Parity Error,
Framing Error or Break
Interrupt
Reads the Line Status
Register
0
1
0
0
Second
Receiver Data
Available
Receiver Data Available or
Trigger Level Reached
Reads the Receiver Buffer
Register or the FIFO has
Dropped Below the
threshold value
1
1
0
0
Second
Character
Timeout Indication
No characters have been
read from or written to the
Rx FIFO during
programming time interval,
and the Rx FIFO is not
empty
Reads The Receiver Buffer
Register
0
0
1
0
Third
Transmitter
Holding Register
Empty
Ready to accept new data
for transmission
Reads the IIR Register or (if
source of interrupt) Writes
To The Transmitter Holding
Register
0
0
0
0
Fourth
Modem Status
Clear to Send, Data Set
Ready, Ring Indicator or
Data Carrier Detected
Reads the Modem Status
Register
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