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ST19WP18 Datasheet(PDF) 4 Page - STMicroelectronics |
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ST19WP18 Datasheet(HTML) 4 Page - STMicroelectronics |
4 / 5 page ST19WP18 4/5 PIN AND SIGNAL OVERVIEW Figure 4. Pinout description Table 1. Signal description Signal Type Description LAD[3:0] Bidir Multiplexed Command, Address and Data (see LPC Interface Spec) LPCPD# Input Power Down indicates that the peripheral should prepare for power to be removed from the LPC i/F devices. Actual power removal is system dependent (see LPC Inter- face Spec) LCLK Input Clock Same 33Mhz clock as PCI clock on the host. Same clock phase with typical PCI skew. (see LPC Interface Spec) LFRAME# Input Frame indicates start of a new cycle, termination of broken cycle (see LPC Interface Spec) LRESET# Input Reset same as PCI Reset on the host (see LPC Interface Spec) SERIRQ Bidir Serialized IRQ is used by TPM to handle interrupt support (see LPC Interface Spec) GPIO5/CLKRUN# Bidir General Purpose IO, weak internal pull-up fully configurable by Software CLKRUN# same as PCI CLKRUN#. Only needed by peripherals that need DMA or bus mastering in a system that can stop the PCI bus (generally in mobile systems) PP Input Physical Presence, active high, internal pull-down. Used to indicate Physical Pres- ence to the TPM GPIO[4:1] Bidir General Purpose IOs with weak internal pull-up fully configurable by Software IO Bidir Bidirectional IO ISO 7816-2 compliant serial port VPS Input 3.3v Power supply. VPS has to be connected to 3.3v DC power rail supplied by the motherboard GND Input Zero volts ground reference. GND has to be connected to the main motherboard ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 GPIO1 GPIO2 IO GND NC GPIO3 PP NC GPIO4 VPS GND NC NC NC LPCPD# SERIRQ LAD0 NC VPS LAD1 LFRAME# LCLK LAD2 NC GPIO5/CLKRUN# LRESET# GND LAD3 TSSOP28 |
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