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IDT72V7250L10 Datasheet(PDF) 10 Page - Integrated Device Technology

Part # IDT72V7250L10
Description  3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

IDT72V7250L10 Datasheet(HTML) 10 Page - Integrated Device Technology

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COMMERCIALTEMPERATURERANGE
IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO
512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72
PROGRAMMING FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable. TheIDT72V7230/
72V7240/72V7250/72V7260/72V7270/72V7280/72V7290/72V72100 have
internalregistersfortheseoffsets. Thereareeightdefaultoffsetvaluesselectable
during Master Reset. These offset values are shown in Table 2. Offset values
can also be programmed into the FIFO in one of two ways; serial or parallel
loadingmethod. Theselectionoftheloadingmethodisdoneusingthe
LD(Load)
pin. During Master Reset, the state of the
LDinputdetermineswhetherserial
or parallel flag offset programming is enabled. A HIGH on
LD during Master
Resetselectsserialloadingofoffsetvalues. ALOWon
LDduringMasterReset
selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q0-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3,Programmable Flag Offset Programming Sequence, summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
For a more detailed description, see discussion that follows.
Theoffsetregistersmaybeprogrammed(andreprogrammed)anytimeafter
Master Reset, regardless of whether serial or parallel programming has been
selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72V7230/72V7240/72V7250/72V7260/72V7270/72V7280/
72V7290/72V72100 can be configured during the Master Reset cycle with
either synchronous or asynchronous timing for
PAF andPAE flags by use of
the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK. Fordetailtimingdiagrams,seeFigure23forsynchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.
PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK. Fordetailtimingdiagrams,seeFigure
25 for asynchronous
PAF timingandFigure26forasynchronousPAEtiming.
IDT72V7230, 72V7240
LD
FSEL1
FSEL0
Offsets n,m
LH
L
511
L
L
H
255
L
L
L
127
LH
H
63
HL
L
31
HH
L
15
HL
H
7
HH
H
3
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial(3)
L
X
X
Parallel(4)
IDT72V7250, 72V7260, 72V7270, 72V7280
LD
FSEL1
FSEL0
Offsets n,m
H
L
L
1,023
LH
L
511
L
L
H
255
L
L
L
127
LH
H
63
HH
L
31
HL
H
15
HH
H
7
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial(3)
L
X
X
Parallel(4)
IDT72V7290, 72V72100
LD
FSEL1
FSEL0
Offsets n,m
L
H
L
16,383
L
L
H
8,191
L
H
H
4,095
H
H
L
2,047
H
L
L
1,023
HL
H
511
HHH
255
LLL
127
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial(3)
L
X
X
Parallel(4)
TABLE 2 — DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.


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