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IDT72V7270L10 Datasheet(PDF) 6 Page - Integrated Device Technology |
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IDT72V7270L10 Datasheet(HTML) 6 Page - Integrated Device Technology |
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6 / 42 page  6 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 Symbol Name I/O Description PIN DESCRIPTION (CONTINUED) EF/OR Empty Flag/ O In the IDT Standard mode, the EF functionisselected. EFindicateswhetherornottheFIFOmemoryisempty. Output Ready InFWFTmode,the OR functionisselected. ORindicateswhetherornotthereisvaliddataavailableattheoutputs. PAF Programmable O PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in Almost-FullFlag the Full Offset register. PAF goes LOW if the number of free locations in the FIFO memory is less than or equal to m. PAE Programmable O PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty Almost-Empty Offset register. PAE goes HIGH if the number of Flag words in the FIFO memory is greater than or equal to offsetn. HF Half-Full Flag O HF indicates whether the FIFO memory is more or less than half-full. Q0–Q71 DataOutputs O Data outputs for an 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused output pins should not be connected. Data Outputs are not 5V tolerant regardless of the state of the OE and RCS. TCK(1) JTAG Clock I Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND. TDI(1) JTAG Test Data Input I One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected. TDO(1) JTAG Test Data Output O One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation, test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and SHIFT-IR controller states. TMS(1) JTAG Mode Select I TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected. TRST(1) JTAG Reset I TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles. If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND. NOTE: 1. These pins are for the JTAG port. Please refer to pages 22-25 and Figures 5-7. |
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