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IDT72V7230L15 Datasheet(PDF) 5 Page - Integrated Device Technology |
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IDT72V7230L15 Datasheet(HTML) 5 Page - Integrated Device Technology |
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5 / 42 page  5 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 PIN DESCRIPTION Symbol Name I/O Description D0–D71 Data Inputs I Data inputs for a 72-, 36- or 18-bit bus. When in 36- or 18-bit mode, the unused input pins should be tied LOW. MRS Master Reset I MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringMasterReset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations, one of eight programmableflagdefaultsettings,serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endian format, zero latency timing mode, interspersed parity, and synchronous versus asynchronous programmable flagtimingmodes. PRS PartialReset I PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringPartialReset, the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings are all retained. RT Retransmit I RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to HIGH in FWFT mode) and does not disturb the write pointer, programming method, existing timing mode or programmable flag settings. RT is useful to reread data from the first physical location of the FIFO. FWFT/SI First Word Fall I DuringMasterReset,selectsFirstWordFallThroughorIDTStandardmode.AfterMasterReset,thispinfunctions Through/Serial In as a serial input for loading offset registers. OW OutputWidth I This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration. IW InputWidth I This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration. BM Bus-Matching I BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size configuration. BE Big-Endian/ I During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset Little-Endian willselectLittle-Endianformat. RM RetransmitTiming I During Master Reset, a LOW on RM will select zero latency Retransmit timing Mode. A HIGH on RM will select Mode normal latency mode. PFM Programmable I During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on Flag Mode PFM will select Synchronous Programmable flag timing mode. IP Interspersed Parity I During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed Parity mode. FSEL0 Flag Select Bit 0 I During Master Reset, this input along with FSEL1 and the LD pin, will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. FSEL1 Flag Select Bit 1 I During Master Reset, this input along with FSEL0 and the LD pin will select the default offset values for the programmable flags PAE and PAF. There are up to eight possible settings available. WCLK WriteClock I When enabled by WEN,therisingedgeofWCLKwritesdataintotheFIFOandoffsetsintotheprogrammable registers for parallel programming. WEN WriteEnable I WEN enables WCLK for writing data into the FIFO memory and offset registers. RCLK Read Clock I When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from the programmable registers. ( RCS mustbeactive). REN Read Enable I REN enables RCLK for reading data from the FIFO memory and offset registers. (RCS must be active). OE OutputEnable I OE provides asynchronous control of the output impedance of Qn.During a Master or Partial Reset the OE input is the only input that provide High-Impedance control of the data outputs. RCS Read Chip Select I RCSprovidessynchronouscontrolof thereadportandoutputimpedanceofQn,synchronoustoRCLK.During a Master or Partial Reset the RCS input is don’t care, if OE is LOW the data outputs will be Low-Impedance regardless of RCS. SCLK Serial Input Clock I when enabled by SEN, the rising edge of SCLK writes one bit of data (present on the SI input), into the programmable register for serial programming. SEN Serial Enable I SENenablesserialloadingofprogrammableflagoffsets. LD Load I This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1, determines one of eight default offset values for the PAEandPAFflags,alongwiththemethodbywhichthese offsetregisterscanbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,thispinenableswriting to and reading from the offset registers. FF/IR Full Flag/ O In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. Input Ready In the FWFT mode, the IRfunctionisselected. IRindicateswhetherornotthereisspaceavailableforwriting to the FIFO memory. |
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