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IDT72V7240L15 Datasheet(PDF) 3 Page - Integrated Device Technology |
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IDT72V7240L15 Datasheet(HTML) 3 Page - Integrated Device Technology |
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3 / 42 page  3 COMMERCIALTEMPERATURERANGE IDT72V7230/7240/7250/7260/7270/7280/7290/72100 3.3V HIGH DENSITY SUPERSYNC IITM FIFO 512 x 72, 1K x 72, 2K x 72, 4K x 72, 8K x 36, 16K x 72, 32K x 72, 64K x 72 DESCRIPTION (CONTINUED) Figure 1. Single Device Configuration Signal Flow Diagram and Read Enable ( REN)input. DataisreadfromtheFIFOoneveryrisingedge of RCLK when REN is asserted. An Output Enable (OE) input is provided for three-state control of the outputs. A Read Chip Select ( RCS) input is also provided for synchronous enable and disable of the read port control input, REN. TheRCSinputissynchronized tothereadclock,andalsoprovidesthree-statecontroloftheQnoutputs.When RCS is disable, REN will be disabled internally and data outputs will be in High-Impedancestate. The frequencies of both the RCLK and the WCLK signals may vary from 0 tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency of the one clock input with respect to the other. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through (FWFT) mode. InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating RENandenablingarisingRCLKedge, will shift the word from internal memory to the data output lines. In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. A RENdoes not have to be asserted for accessing the first word. However, subsequent words written to the FIFO do require a LOW on REN for access. The state of the FWFT/SI input during Master Reset determines the timing mode in use. For applications requiring more data storage capacity than a single FIFO canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs in series (i.e. the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required. These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready), FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable Almost-Emptyflag)and PAF(ProgrammableAlmost-Fullflag). TheEFandFF functions are selected in IDT Standard mode. The IR and OR functions are selected in FWFT mode. HF, PAE and PAF are always available for use, irrespective of timing mode. PAE and PAFcanbeprogrammedindependentlytoswitchatanypointin memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso provided, so that PAEcanbesettoswitchatapredefinednumberoflocations from the empty boundary and the PAF threshold can also be set at similar predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring Master Reset by the state of the FSEL0, FSEL1, and LD pins. For serial programming, SEN together with LD on each rising edge of SCLK, are used to load the offset registers via the Serial Input (SI). For parallel programming, WENtogetherwith LD oneachrisingedgeofWCLK,areused to load the offset registers via Dn. REN together with LD on each rising edge ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether serial or parallel offset loading has been selected. (x72, x36, x18) DATA OUT (Q0 - Qn) (x72, x36, x18) DATA IN (D0 - Dn) MASTER RESET ( MRS) READ CLOCK (RCLK) READ ENABLE ( REN) OUTPUT ENABLE ( OE) EMPTY FLAG/OUTPUT READY ( EF/OR) PROGRAMMABLE ALMOST-EMPTY ( PAE) WRITE CLOCK (WCLK) WRITE ENABLE ( WEN) LOAD ( LD) FULL FLAG/INPUT READY ( FF/IR) PROGRAMMABLE ALMOST-FULL ( PAF) IDT 72V7230 72V7240 72V7250 72V7260 72V7270 72V7280 72V7290 72V72100 PARTIAL RESET ( PRS) FIRST WORD FALL THROUGH/SERIAL INPUT (FWFT/SI) RETRANSMIT ( RT) 4680 drw03 HALF-FULL FLAG ( HF) SERIAL ENABLE( SEN) INPUT WIDTH (IW) OUTPUT WIDTH (OW) BIG-ENDIAN/LITTLE-ENDIAN ( BE) INTERSPERSED/ NON-INTERSPERSED PARITY (IP) BUS- MATCHING (BM) SERIAL IN CLOCK(SCLK) JTAG CLOCK (TCLK) JTAG RESET ( TRST) JTAG MODE (TMS) (TDO) (TDI) READ CHIP SELECT ( RCS) |
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