7
A6155
well as the current consumption of the divider itself. Low
resistor values will need more current, but high resistor
values will make the reset threshold less accurate at
high temperature, due to a possible leakage current at
the V
IN input. The sum of the two resistors should stay
below 300 kΩ. The formula is: VRESET = VREF *(1 + R1/R2).
Example: choosing R
1 = 100 k
Ω and R2 = 39 kΩ will
result in a V
DD reset threshold of 4.54 V (typ.).
At power-up the reset output (RES) is held low (see
Fig. 5). After INPUT reaches 3.36 V (and so OUTPUT
reach-es at least 3 V) and V
IN becomes greater than VREF,
the RES output is held low for an additional power-on-
reset (POR) delay which is equal to the watchdog time
T
WD (typically 100 ms with an external resistor of 110 kΩ
con-nected at R pin). The POR delay prevents repeated
togging of RES even if V
IN and the INPUT voltage drops
out and recovers. The POR delay allows the micropro-
cessor’s crystal oscillator time to start and stabilize and
ensures correct recognition of the reset signal to the
microprocessor.
The RES output goes active low generating the power-
down reset whenever V
IN falls below VREF. The sensitivity
or reaction time of the internal comparator to the vol-
tage level on V
IN is typically 5 µs.
Timer Programming
The on-chip oscillator with an external resistor R
EXT con-
nected between the R pin and V
SS (see Fig. 9) allows the
user to adjust the power-on reset (POR) delay,
watchdog time T
WD and with this also the closed and
open time windows as well as the watchdog reset pulse
width (T
WD/40).
With R
EXT = 110 kΩ typical values are:
-Power-on reset delay: T
POR is 100 ms
-Watchdog time:
T
WD is 100 ms
-Closed window:
T
CW is
80 ms
-Open window:
T
OW is
40 ms
-Watchdog reset:
T
WDRis 2.25 ms
Note the current consumption increases as the fre-
quency increases.
Watchdog Timeout Period Description
The watchdog timeout period is divided into two parts, a
“closed” window and an “open” window (see Fig. 4) and
is defined by two parameters, T
WD and the Open Window
Percentage (OWP).
The closed window starts just after the watchdog timer
resets and is defined by T
CW = TWD – OWP(TWD).
The open window starts after the closed time window
finishes and lasts till T
WD + OWP(TWD).The open window
time is defined by T
OW = 2 x OWP (TWD)
For example if T
WD = 100 ms (actual value) and OWP =
± 20% this means the closed window lasts during first
the 80 ms (T
CW = 80 ms = 100 ms – 0.2 (100 ms)) and
the open window the next 40 ms (T
OW = 2 x 0.2 (100 ms)
= 40 ms). The watchdog can be serviced between
80 ms and 120 ms after the timer reset. However as the
time base is ± 10% accurate, software must use the
following calculation for servicing signal TCL during the
open window:
Related to curves (Fig. 10 to Fig. 21), especially Fig. 20
and Fig. 21, the relation between T
WD and REXT could
easely be defined. Let us take an example describing
the variations due to production and temperature:
1. Choice, T
WD = 26 ms.
2. Related to Fig. 21, the coefficient (T
WD to REXT) is
1.025 where R
EXT is in kΩ and TWD in ms.
3. R
EXT (typ.) = 26 x 1.025 =26.7 kΩ.
4.
26 ms at +25 °C
a)(26 − 10% = 23.4 ms) (26 + 10% = 28.6 ms)a)
b)(23.4 − 5% = 22.2 ms)
(28.6 + 5% = 30.0 ms)b)
min.: (30.0 − 20% = 24.0 ms) max.: (22.2 + 20% = 26.7 ms)
Typical TCL period of
(24.0 + 26.7) / 2 = 25.4 ms
The ratio between T
WD = 26 ms and the (TCL period)
= 25.4 ms is 0.975.
Then the relation over the production and the full
temperature range is, TCL period = 0.975 x T
WD
or
TCL period =
, as typical value.
a)While PRODUCTION value unknown for the custo-
mer when R
EXT ≠ 110 kΩ.
b)While operating TEMPERATURE range
-40 °C ≤ TJ ≤ +85 °C.
5. If you fixed a TCL period = 26 ms
⇒ REXT =
= 27.3 kΩ.
If during your production the T
WD time can be mea-
sured at T
J = + 25 °C and the µC can adjust the TCL
period, then the TCL period range will be much larger
for the full operating temperature.
Timer Clearing and RES Action
The watchdog circuit monitors the activity of the proces-
sor. If the user’s software does not send a pulse to the
TCL input within the programmed open window timeout
period a short watchdog RES pulse is generated which
is equal to T
WD /40 = 2.5 ms typically (see Fig. 6).
With the open window constraint new security is added
to conventional watchdogs by monitoring both software
cycle time and execution. Should software clear the
watchdog too quickly (incorrect cycle time) or too slowly
(incorrect execution) it will cause the system to be reset.
If software is stuck in a loop which includes the routine
to clear the watchdog then a conventional watchdog
would not make a system reset even though software is
malfunctioning; the A6155 would make a system reset
because the watchdog would be cleared too quickly.
If no TCL signal is applied before the closed and open
windows expire, RES will start to generate square waves
of period (T
CW + TOW + TWDR). The watchdog will remain
in this state until the next TCL falling edge appears
0.975 x R
EXT
1.025
26 x 1.025
0.975
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