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M36LLR8760B1 Datasheet(PDF) 7 Page - STMicroelectronics |
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M36LLR8760B1 Datasheet(HTML) 7 Page - STMicroelectronics |
7 / 19 page 7/19 M36LLR8760T1, M36LLR8760D1, M36LLR8760M1, M36LLR8760B1 SIGNAL DESCRIPTIONS See Figure 2., Logic Diagram and Table 1., Signal Names, for a brief overview of the signals connect- ed to this device. Address Inputs (A0-A23). Addresses A0-A21 are common inputs for the Flash memory and PSRAM components. A22 is common to the two Flash memory components whereas A23 is an ad- dress input for the 256 Mbit Flash memory compo- nent only. The Address Inputs select the cells in the memory array to access during Bus Read operations. Dur- ing Bus Write operations they control the com- mands sent to the Command Interface of the internal state machine. The Flash memories are accessed through the Chip Enable signal (EF) and through the Write Enable signal (WF), while the PSRAM is accessed through the Chip Enable sig- nal (EP) and the Write Enable signal (WP). It is not allowed to have EF Low, and EP Low at the same time. Data Input/Output (DQ0-DQ15). The Data I/O output the data stored at the selected address dur- ing a Bus Read operation or input a command or the data to be programmed during a Bus Write op- eration. For the PSRAM component, the upper Byte Data Inputs/Outputs (DQ8-DQ15) carry the data to or from the upper part of the selected address when Upper Byte Enable (UBP) is driven Low. The lower Byte Data Inputs/Outputs (DQ0-DQ7) carry the data to or from the lower part of the selected ad- dress when Lower Byte Enable (LBP) is driven Low. When both UBP and LBP are disabled, the Data Inputs/ Outputs are high impedance. Latch Enable (L). The Latch Enable pin is com- mon to the Flash memory and PSRAM compo- nents. For details of how the Latch Enable signal be- haves, please refer to the datasheets of the re- spective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respec- tively. Clock (K). The Clock input pin is common to the Flash memory and PSRAM components. For details of how the Clock signal behaves, please refer to the datasheets of the respective memory components: M69KB096AA for the PSRAM and M30L0R8000(T/B)0 and M58LR128GT/B for Flash 1 and Flash 2, respec- tively. Wait (WAIT). WAIT is an output pin common to the Flash memory and PSRAM components. How- ever the WAIT signal does not behave in the same way for the PSRAM and the Flash memories. For details of how it behaves, please refer to the M69KB096AA datasheet for the PSRAM and to the M30L0R8000T/B0 and M58LR128GT/B datasheets for Flash 1 and Flash 2, respectively. Flash Chip Enable Inputs (EF1, EF2). The Flash Chip Enable inputs activate the control logic, input buffers, decoders and sense amplifiers of the Flash memory component selected (EF1 is used to select Flash 1, EF2 is used to select Flash 2). When Chip Enable is Low, VIL, and Reset is High, VIH, the device is in active mode. When Chip En- able is at VIH the corresponding Flash memory are deselected, the outputs are high impedance and the power consumption is reduced to the standby level. It is not allowed to have EF1 at VIL, EF2 at VIL and EP at VIL at the same time. Only one memory com- ponent can be enabled at a time. Flash Output Enable Inputs (GF1, GF2). The Output Enable pins control the data outputs during Flash memory Bus Read operations. Flash Write Enable (WF). The Write Enable controls the Bus Write operation of the Flash memories’ Command Interface. The data and ad- dress inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Flash Write Protect (WPF). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, VIL, Lock-Down is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at High, VIH, Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (See the Lock Status Table in the M30L0R8000(T/B)0 and M58LR128GT/B datasheets). Flash Reset (RPF). The Reset input provides a hardware reset of the Flash memories. When Re- set is at VIL, the memory is in Reset mode: the out- puts are high impedance and the current consumption is reduced to the Reset Supply Cur- rent IDD2. Refer to Table 6., Flash 1 DC Character- istics - Currents, for the value of IDD2. After Reset all blocks are in the Locked state and the Configu- ration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting Reset mode the device enters Asynchronous Read mode, but |
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