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TFDS6502E-TR3 Datasheet(PDF) 10 Page - Vishay Siliconix |
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TFDS6502E-TR3 Datasheet(HTML) 10 Page - Vishay Siliconix |
10 / 17 page TFDU6102E/TFDS6402/TFDS6502E/TFDT6502E Vishay Semiconductor Rev. B1.6, 02–Nov–00 10 www.vishay.com Document Number 82526 Setting to the Lower Bandwidth Mode (2.4 kbit/s to 115.2 kbit/s) 1. Set SD/MODE input to logic “HIGH”. 2. Set Txd input to logic “LOW”. Wait ts ≥ 200 ns. 3. Set SD/MODE to logic “LOW” (this negative edge latches state of Txd, which determines speed setting). 4. Txd must be held for th ≥ 200 ns. Txd is now enabled as normal Txd input for the lower bandwidth mode. Recommended SMD Pad Layout The leads of the device should be soldered in the center position of the pads. 16524 0.6 ( ≤ 0.7) 7 x 1 = 7 8 1 1 2.5 ( ≥ 2.0) Figure 7. TFDU6102E BabyFace (Universal) Figure 8. TFDS6402 (Dracula) |
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