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709179L7PFI Datasheet(PDF) 3 Page - Integrated Device Technology |
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709179L7PFI Datasheet(HTML) 3 Page - Integrated Device Technology |
3 / 15 page 6.42 IDT709179L High-Speed 32K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges 3 Preliminary NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table IRead/Write and Enable Control(1,2,3) OE CLK CE0 CE1 R/ W I/O0-8 Mode X ↑ H X X High-Z Deselected—Power Down X ↑ X L X High-Z Deselected—Power Down X ↑ LH L DATAIN Write L ↑ L HHDATAOUT Read H X L H X High-Z Outputs Disabled 5644 tbl 02 Pin Names Left Port Right Port Names CE0L, CE1L CE0R, CE1R Chip Enables R/WL R/WR Read/Write Enable OEL OER Output Enable A0L - A14L A0R - A14R Address I/O0L - I/O8L I/O0R - I/O8R Data Input/Output CLKL CLKR Clock ADSL ADSR Address Strobe CNTENL CNTENR Counter Enable CNTRSTL CNTRSTR Counter Reset FT/PIPEL FT/PIPER Flow-Through/Pipeline VCC Power GND Ground 5644 tbl 01 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0 and CE1. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1. 6. While an external address is being loaded ( ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily. Truth Table IIAddress Counter Control(1,2,6) Address Previous Address Addr Used CLK(6) ADS CNTEN CNTRST I/O(3) MODE An X A n ↑ L (4) XH DI/O (n) E xternal A d dres s Use d XA n A n + 1 ↑ H L (5) HDI/O(n+ 1) Co unte r E nab le d — Inte rnal A d dres s ge ne ration X A n + 1 A n + 1 ↑ HH H DI/O(n+1) E xte rnal A d d re ss B lo cke d — Co unte r dis ab led (A n + 1 re used ) XX A o ↑ XX L (4) DI/O(0) Co unter Re se t to A d dress 0 5644 tbl 03 |
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