K6R3024V1D

CMOS SRAM

Revision 1.0

- 2 -

December 2001

for AT&T

128K x 24 Bit High-Speed CMOS Static RAM(3.3V Operating)

The K6R3024V1D is a 3,145,728-bit high-speed Static Random

Access Memory organized as 131,072 words by 24 bits. The

K6R3024V1D uses 24 common input and output lines and has an

output enable pin which operates faster than address access

time at read cycle. The device is fabricated using SAMSUNG’s

advanced CMOS process and designed for high-speed circuit

technology. It is particularly well suited for use in high-density

high-speed system applications. The K6R3024V1D is a three

megabit static RAM constructed on an multilayer laminate sub-

strate using three 3.3V, 128K x 8 static RAMS encapsulated in a

Ball Grid Array(BGA).

GENERAL DESCRIPTION

FEATURES

• Fast Access Time 9,10,12ns

• Power Dissipation

Standby (TTL)

: 40mA(Max.)

(CMOS) : 15mA(Max.)

Operating K6R3024V1D-09 : 170mA(Max.)

K6R3024V1D-10 : 150mA(Max.)

K6R3024V1D-12 : 130mA(Max.)

Single 3.3V Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• 119(7x17)Pin Ball Grid Array Package(14mmx22mm)

• Operating in Commercial and Industrial Temperature range.

128K x 8

FUNCTIONAL BLOCK DIAGRAM

8

A0-16

ORDERING INFORMATION

K6R3024V1D-HC09/HC10/HC12

Commercial Temp.

K6R3024V1D-HI09/HI10/HI12

Industrial Temp.

CS1

WE

OE

PIN FUNCTION

Pin Name

Pin Function

Addresses Inputs

WE

Write Enable

Chip Select

OE

Output Enable

Data Inputs/Outputs

Power(+3.3v)

Ground

NC

No Connection

SRAM

128K x 8

SRAM

128K x 8

SRAM

8

8

17

CS2

CS3

K6R3024V1D

1

2

3

4

5

6

7

A

NC

A

A

A

A

A

NC

B

NC

A

A

A

A

NC

C

I/O

NC

NC

NC

I/O

D

I/O

I/O

E

I/O

I/O

F

I/O

I/O

G

I/O

I/O

H

I/O

I/O

J

K

I/O

I/O

L

I/O

I/O

M

I/O

I/O

N

I/O

I/O

P

I/O

I/O

R

I/O

NC

NC

NC

NC

NC

I/O

T

NC

A

A

WE

A

A

NC

U

NC

A

A

OE

A

A

NC