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PIN DESCRIPTION

12

11

10

9

8

7

1

2

3

4

5

6

VDD

VREFH

VREFL

VFB

VOUT

GND

CLR

SYNC

SCLK

SDIN

SDO

IOVDD

DRN PACKAGE

(TOP VIEW)

DAC7551

SLAS441 – MARCH 2005

Terminal Functions

TERMINAL

DESCRIPTION

NO.

NAME

1

VDD

Analog voltage supply input

2

VREFH

Positive reference voltage input

3

VREFL

Negative reference voltage input

4

VFB

DAC amplifier sense input.

5

VOUT

Analog output voltage from DAC

6

GND

Ground

7

CLR

Asynchronous input to clear the DAC registers. When CLR is low, the DAC register is set to 000H and the output

voltage to 0 V.

8

SYNC

Frame synchronization input. The falling edge of the SYNC pulse indicates the start of a serial data frame shifted out

to the DAC7551.

9

SCLK

Serial clock input

10

SDIN

Serial data input

11

SDO

Serial data output

12

IOVDD

I/O voltage supply input

6