PARAMETER

UNIT

TEST CONDITIONS

ns

tdos

tconv

tpd

CL = 100 pF

ns

ADC0834A, ADC0838A, ADC0834B, ADC0838B

A/D PERIPHERALS WITH SERIAL CONTROL

SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986

POST OFFICE BOX 655303

9

AI, AC SUFFIX

BI, BC SUFFIX

MIN

TYP

MAX

MIN

TYP

MAX

Supply-voltage variation error

VCC = 4.75 V to 5.25 V

±1/16

±1/4

±1/16

±1/4

LSB

Total unadjusted error (see Note 6)

Vref = 5 V,

TA = MIN to MAX

±1

±1/2

LSB

Common-mode error

Differential mode

±1/16

±1/4

±1/16

±1/4

LSB

Change in zero-error from VCC = 5 V to internal

zener diode operation (see Note 2)

II = 15 mA at V+ pin,

Vref = 5 V, VCC open

1

1

LSB

Propagation delay time, output

MSB-first data

650

1500

650

1500

data after CLK

↓, (see Note 7)

LSB-first data

250

600

250

600

Output disable time,

CL = 10 pF, RL = 10 kΩ

125

250

125

250

DO or SARS after CS

↑

CL = 100 pF, RL = 2 kΩ

500

500

Conversion time (multiplexer addressing

time not included)

8

8

clock

periods

† All parameters are measured under open-loop conditions with zero common-mode input voltage. For conditions shown as MIN or MAX, use the

appropriate value specified under recommended operating conditions.

NOTES:2. Internal zener diodes are connected from the VCC input to ground and from the V+ input to ground. The breakdown voltage of each zener

diode is approximately 7 V. One zener diode can be used as a shunt regulator and connects to VCC through a regular diode. When

the voltage regulator powers the converter, this zener and regular diode combination ensures that the VCC input (6.4 V) is less than

the zener breakdown voltage. A series resistor is recommended to limit current into the V+ input.

6. Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors.

7. The most significant bit (MSB) data is output directly from the comparator and therefore requires additional delay to allow for comparator response

time.

PARAMETER MEASUREMENT INFORMATION

50%

tsu

th

th

tsu

50%

VCC

GND

GND

GND

0.4 V

0.4 V

2 V

2 V

DI

0.4 V

CS

CLK

VCC

VCC

Figure 1. Data Input Timing