ADC0834A, ADC0838A, ADC0834B, ADC0838B

A/D PERIPHERALS WITH SERIAL CONTROL

SLAS007 – AUGUST 1985 – REVISED OCTOBER 1986

POST OFFICE BOX 655303

3

functional description

The ADC0834 and ADC0838 use a sample data comparator structure that converts differential analog inputs

by a successive-approximation routine. Operation of both devices is similar with the exception of SE, an analog

common input, and multiplexer addressing. The input voltage to be converted is applied to a channel terminal

and is compared to ground (single-ended), to an adjacent input (differential), or to a common terminal

(pseudo-differential) that can be an arbitrary voltage. The input terminals are assigned a positive (+) or negative

(–) polarity. If the signal input applied to the assigned positive terminal is less than the signal on the negative

terminal, the converter output is all zeros.

Channel selection and input configuration are under software control using a serial data link from the controlling

processor. A serial-communication format allows more functions to be included in a converter package with no

increase in size. In addition, it eliminates the transmission of low-level analog signals by locating the converter

at the analog sensor and communicating serially with the controlling processor. This process returns noise-free

digital data to the processor.

A particular input configuration is assigned during the multiplexer addressing sequence. The multiplexer

address is shifted into the converter through the data input (DI) line. The multiplexer address selects the analog

inputs to be enabled and determines whether the input is single-ended or differential. When the input is

differential, the polarity of the channel input is assigned. Differential inputs are assigned to adjacent channel

pairs . For example, channel 0 and channel 1 may be selected as a differential pair. These channels cannot act

differentially with any other channel. In addition to selecting the differential mode, the polarity may also be

selected. Either channel of the channel pair may be designated as the negative or positive input.

The common input on the ADC0838 can be used for a pseudo-differential input. In this mode, the voltage on

the common input is considered to be the negative differential input for all channel inputs. This voltage can be

any reference potential common to all channel inputs. Each channel input can then be selected as the positive

differential input. This feature is useful when all analog circuits are biased to a potential other than ground.

A conversion is initiated by setting CS low, which enables all logic circuits. CS must be held low for the complete

conversion process. A clock input is then received from the processor. On each low-to-high transition of the clock

input, the data on DI is clocked into the multiplexer address shift register. The first logic high on the input is the

start bit. A 3- to 4-bit assignment word follows the start bit. On each successive low-to-high transition of the clock

input, the start bit and assignment word are shifted through the shift register. When the start bit is shifted into

the start location of the multiplexer register, the input channel is selected and conversion starts. The SAR Status

output (SARS) goes high to indicate that a conversion is in progress, and DI to the multiplexer shift register is

disabled the duration of the conversion.

An interval of one clock period is automatically inserted to allow the selected multiplexed channel to settle. The

data output DO comes out of the high-impedance state and provides a leading low for this one clock period of

multiplexer settling time. The SAR comparator compares successive outputs from the resistive ladder with the

incoming analog signal. The comparator output indicates whether the analog input is greater than or less than

the resistive ladder output. As the conversion proceeds, conversion data is simultaneously output from the DO

output pin, with the most significant bit (MSB) first.

After eight clock periods, the conversion is complete and the SARS output goes low.

The ADC0834 outputs the least-significant-bit-first data after the MSB-first data stream. If SE is held high on

the ADC0838, the value of the least significant bit (LSB) will remain on the data line. When SE is forced low,

the data is then clocked out as LSB-first data. (To output LSB first, SE must first go low, then the data stored

in the 9-bit shift register outputs LSB first.) When CS goes high, all internal registers are cleared. At this time

the output circuits go to the high-impedance state. If another conversion is desired, CS must make a high-to-low

transition followed by address information.