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MC68EC020RP16 Datasheet(PDF) 7 Page - Motorola, Inc |
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MC68EC020RP16 Datasheet(HTML) 7 Page - Motorola, Inc |
7 / 306 page 9/29/95 SECTION 1: OVERVIEW UM Rev 1 MOTOROLA M68020 USER’S MANUAL xi TABLE OF CONTENTS (Continued) Paragraph Page Number Title Number 7.3.1 Response CIR .....................................................................................7-24 7.3.2 Control CIR ..........................................................................................7-24 7.3.3 Save CIR .............................................................................................7-25 7.3.4 Restore CIR .........................................................................................7-25 7.3.5 Operation Word CIR ............................................................................7-25 7.3.6 Command CIR .....................................................................................7-25 7.3.7 Condition CIR ......................................................................................7-26 7.3.8 Operand CIR .......................................................................................7-26 7.3.9 Register Select CIR .............................................................................7-27 7.3.10 Instruction Address CIR .......................................................................7-27 7.3.11 Operand Address CIR .........................................................................7-27 7.4 Coprocessor Response Primitives ..........................................................7-27 7.4.1 ScanPC ...............................................................................................7-28 7.4.2 Coprocessor Response Primitive General Format .............................. 7-28 7.4.3 Busy Primitive ......................................................................................7-30 7.4.4 Null Primitive ........................................................................................7-31 7.4.5 Supervisor Check Primitive .................................................................7-33 7.4.6 Transfer Operation Word Primitive ......................................................7-33 7.4.7 Transfer from Instruction Stream Primitive ..........................................7-34 7.4.8 Evaluate and Transfer Effective Address Primitive ............................. 7-35 7.4.9 Evaluate Effective Address and Transfer Data Primitive ..................... 7-35 7.4.10 Write to Previously Evaluated Effective Address Primitive ..................7-37 7.4.11 Take Address and Transfer Data Primitive..........................................7-39 7.4.12 Transfer to/from Top of Stack Primitive ...............................................7-40 7.4.13 Transfer Single Main Processor Register Primitive .............................7-40 7.4.14 Transfer Main Processor Control Register Primitive ...........................7-41 7.4.15 Transfer Multiple Main Processor Registers Primitive .........................7-42 7.4.16 Transfer Multiple Coprocessor Registers Primitive .............................7-42 7.4.17 Transfer Status Register and ScanPC Primitive..................................7-44 7.4.18 Take Preinstruction Exception Primitive ..............................................7-45 7.4.19 Take Midinstruction Exception Primitive ..............................................7-47 7.4.20 Take Postinstruction Exception Primitive ............................................7-48 7.5 Exceptions ...............................................................................................7-49 7.5.1 Coprocessor-Detected Exceptions ......................................................7-49 7.5.1.1 Coprocessor-Detected Protocol Violations ......................................7-50 7.5.1.2 Coprocessor-Detected Illegal Command or Condition Words ......... 7-51 7.5.1.3 Coprocessor Data-Processing-Related Exceptions .........................7-51 7.5.1.4 Coprocessor System-Related Exceptions .......................................7-51 7.5.1.5 Format Errors ...................................................................................7-52 7.5.2 Main-Processor-Detected Exceptions .................................................7-52 7.5.2.1 Protocol Violations ...........................................................................7-52 7.5.2.2 F-Line Emulator Exceptions .............................................................7-54 |
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