SN65HVD1176

SN75HVD1176

SLLS563C − JULY 2003 − REVISED APRIL 2005

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7

60

250

135

IOS

Voltage

Source

VOS

Output

Current |mA|

t(CFB)

t(TSD)

time

D

Figure 8. Driver Short-Circuit Test Circuit and Waveforms (Short Circuit applied at Time t = 0)

VID

VA

VB

IO

A

B

IB

VO

R

IA

VIC

VA + VB

2

Figure 9. Receiver DC Parameter Definitions

50

Ω

Signal

Generator

CL = 15 pF

50

Ω

Signal

Generator

A

VID

B

R

IO

VO

50%

90%

10%

1.5 V

0 V

VOH

VOL

tPLH

tPHL

tr

tf

Input B

Input A

Output

1.5 V

Figure 10. Receiver Switching Test Circuit and Waveforms

VI = A sin 2pft

1 MHz < f < 50 MHz

100 nF

2.2 k

Ω

Voffset =

−2 V to 7 V

50

Ω

50

Ω

470 nF

RE

R

DE

D

Scope

VR

2.2 k

Ω

VCC

100 nF

GND

A

B

Scope

VR shall be greater than

2 V throughout this test.

Figure 11. Receiver Common-Mode Rejection Test Circuit