Si5022 /Si502 3
Preliminary Rev. 0.46
9
Table 4. AC Characteristics (PLL Characteristics)
(VDD=2.5 V ± 5% for Si5022 or 3.3 V ± 5% for Si5023, TA = –40°C to 85°C)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Jitter Tolerance
(OC-48)*
JTOL(PP)
f = 600 Hz
40
TBD
—
UIPP
f = 6000 Hz
4
TBD
—
UIPP
f = 100 kHz
4
TBD
—
UIPP
f = 1 MHz
0.4
TBD
—
UIPP
Jitter Tolerance
(OC-12 Mode)*
JTOL(PP)
f = 30 Hz
40
TBD
—
UIPP
f = 300 Hz
4
TBD
—
UIPP
f = 25 kHz
4
TBD
—
UIPP
f = 250 kHz
0.4
TBD
—
UIPP
Jitter Tolerance
(OC-3 Mode)*
JTOL(PP)
f = 30 Hz
60
TBD
—
UIPP
f = 300 Hz
6
TBD
—
UIPP
f = 6.5 kHz
6
TBD
—
UIPP
f = 65 kHz
0.6
TBD
—
UIPP
Jitter Tolerance (Gigabit Ethernet)
Receive Data Total Jitter
Tolerance
TJT(PP)
IEEE 802.3z Clause 38.68
600
TBD
—
ps
Jitter Tolerance (Gigabit Ethernet)
Receive Data Deterministic Jitter
Tolerance
DJT(PP)
IEEE 802.3z Clause 38.69
370
TBD
—
ps
RMS Jitter Generation*
JGEN(RMS) with no jitter on serial data
—
3.0
5.0
mUI
Peak-to-Peak Jitter Generation*
JGEN(PP)
with no jitter on serial data
—
25
55
mUI
Jitter Transfer Bandwidth*
JBW
OC-48 Mode
—
—
2.0
MHz
OC-12 Mode
—
—
500
kHz
OC-3 Mode
—
—
130
kHz
Jitter Transfer Peaking*
JP
—
0.03
0.1
dB
Acquisition Time
(Reference clock applied)
TAQ
After falling edge of
PWRDN/CAL
1.45
1.5
1.7
ms
From the return of valid
data
40
60
150
µs
Acquisition Time
(Reference-less operation)
TAQ
After falling edge of
PWRDN/CAL
TBD
TBD
TBD
ms
From the return of valid
data
TBD
TBD
TBD
ms
Reference Clock Range
19.44
—
168.75
MHz
Input Reference Clock Frequency
Tolerance
CTOL
–100
—
100
ppm
Frequency Difference at which
Receive PLL goes out of Lock
(REFCLK compared to the divided
down VCO clock)
TBD
600
TBD
ppm
Frequency Difference at which
Receive PLL goes into Lock (REF-
CLK compared to the divided
down VCO clock)
TBD
300
TBD
ppm
*Note: As defined in Bellcore specifications: GR-253-CORE, Issue 2, December 1995. Using PRBS 223 – 1 data pattern.