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MAX3420E Datasheet(PDF) 6 Page - Maxim Integrated Products |
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MAX3420E Datasheet(HTML) 6 Page - Maxim Integrated Products |
6 / 23 page mode, these status bits are accessed in the normal way, as register bits. The first five registers (R0–R4) access endpoint FIFOs. To access a FIFO, an initial command byte sets the register address and then consecutive reads or writes keep the same register address to access subsequent FIFO bytes. The remaining registers (R5–R20) control the operation of the MAX3420E. Once a register address above R4 is set in the command byte, successive byte reads or writes in the same SPI access cycle ( SS low) increment the register address after every byte read or written. This incrementing operation continues until R20 is accessed. Subsequent byte reads or writes continue to access R20. Note that this auto-incrementing action stops with the next SPI cycle, which establishes a new register address. Addressing beyond R20 is ignored. USB Peripheral Controller with SPI Interface 6 _______________________________________________________________________________________ Table 1. MAX3420E Register Map REG NAME b7 b6 b5 b4 b3 b2 b1 b0 acc R0 EP0FIFO b7b6b5b4b3b2b1b0 RSC R1 EP1OUTFIFO b7b6b5b4b3b2b1b0 RSC R2 EP2INFIFO b7b6b5b4b3b2b1b0 RSC R3 EP3INFIFO b7b6b5b4b3b2b1b0 RSC R4 SUDFIFO b7b6b5b4b3b2b1b0 RSC R5 EP0BC 0b6b5b4b3b2b1b0 RSC R6 EP1OUTBC 0b6b5b4b3b2b1b0 RSC R7 EP2INBC 0b6b5b4b3b2b1b0 RSC R8 EP3INBC 0b6b5b4b3b2b1b0 RSC R9 EPSTALLS 0 ACKSTAT STLSTAT STLEP3IN STLEP2IN STLEP1OUTSTLEP0OUTSTLEP0IN RSC R10 CLRTOGS EP3DISAB EP2DISAB EP1DISAB CTGEP3IN CTGEP2IN CTGEP1OUT 00 RSC R11 EPIRQ 00 SUDAVIRQ IN3BAVIRQ IN2BAVIRQ OUT1DAVIRQ OUT0DAVIRQ IN0BAVIRQ RC R12 EPIEN 00 SUDAVIE IN3BAVIE IN2BAVIE OUT1DAVIE OUT0DAVIE IN0BAVIE RSC R13 USBIRQ URESDNIRQ VBUSIRQ NOVBUSIRQ SUSPIRQ URESIRQ BUSACTIRQ RWUDNIRQ OSCOKIRQ RC R14 USBIEN URESDNIE VBUSIE NOVBUSIE SUSPIE URESIE BUSACTIE RWUDNIE OSCOKIE RSC R15 USBCTL HOSCSTEN VBGATE CHIPRES PWRDOWN CONNECT SIGRWU 0 0 RSC R16 CPUCTL 00 0 0 0 0 0 IE RSC R17 PINCTL EP3INAK EP2INAK EP0INAK FDUPSPIINTLEVEL POSINTGPXBGPXA RSC R18 REVISION 00 0 0 0 0 1 0 R R19 FNADDR 0b6b5b4b3b2b1b0 R R20 IOPINS GPIN3 GPIN2 GPIN1GPIN0 GPOUT3 GPOUT2 GPOUT1 GPOUT0 RSC Note: The acc (access) column indicates how the SPI Master can access the register. R = Read, RC = Read or Clear, RSC = Read, Set, or Clear. Writing to an R register (Read-Only) has no effect. Writing a 1 to an RC bit (Read or Clear) clears the bit. Writing a zero to an RC bit has no effect. |
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