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ISL6271ACR-T Datasheet(PDF) 8 Page - Intersil Corporation |
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ISL6271ACR-T Datasheet(HTML) 8 Page - Intersil Corporation |
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8 / 16 page  8 FN9171.1 Operational Description Initialization Upon application of input power to the ISL6271A, the power good signal (PGOOD) will switch from low to high after four conditions are met - (1) VCC exceeds the power on reset “rising threshold”, (2) the EN pin is high and (3) the LDO input voltage (LVCC) is greater than 1.6V, (4) All three outputs are in regulation. Figure 16 illustrates this start-up sequence. The outputs are powered on under a soft-start regime with the core output voltage defaulting to 1.3V (unless under VID control) and the LDOs at their fixed output levels. Once the outputs are in regulation, the ISL6271A will respond to a voltage change command via the I2C bus. When under VID control (VIDEN = HI), the Vout will rise to a value set by VID pins. The slew rate is always fixed by the soft-start capacitor. Core Regulator Output The ISL6271A core regulator is a synchronous buck regulator that employs an Intersil proprietary switch-mode topology known as Synthetic Ripple Regulation (SRR). The SRR architecture is a derivative of the conventional hysteretic-mode regulator without the inherent noise sensitivities and dependence on output capacitance ESR. The topology achieves excellent transient response and high efficiency over the entire operating load range. Output voltage ripple is typically under 5mV in Continuous Conduction Mode (CCM) and under 10mV in DCM (diode emulation). The output core voltage is derived from the main battery pack (typically a single cell Li-ion battery) and is programmable in 50mV steps between 0.85 and 1.6V. The output regulator set-point is controlled by an on-chip DAC which receives its input either from the I2C bus or the VID input pins (VID0-VID3). Table 1 identifies the VID code states and corresponding output voltage. To minimize core voltage over-shoot and under-shoot between code states, the ISL6271A implements programmable, voltage slew rate control via the I2C bus. The slew rate is a function of the data in the slew rate control register and also the soft-start capacitor; the slew rates in Table 2 assume a soft-start capacitor value of 10nF. Once the regulator has initialized, the IC can be placed in a low quiescent state by pulling low the EN pin. The regulator ‘remembers’ the last programmed voltage level and slew rate after each subsequent EN cycle, and return to the previous set-point once EN is brought high. TABLE 1. VOLTAGE-SET COMMAND BITS I2C DATA BYTE OR VID PINS NOMINAL OUTPUT MSB D3D2D1 LSB D0 XXXX 0000 0.850 XXXX 0001 0.900 XXXX 0010 0.950 XXXX 0011 1.000 XXXX 0100 1.050 XXXX 0101 1.100 XXXX 0110 1.150 XXXX 0111 1.200 XXXX 1000 1.250 XXXX 1001 1.300 XXXX 1010 1.350 XXXX 1011 1.400 XXXX 1100 1.450 XXXX 1101 1.500 XXXX 1110 1.550 XXXX 1111 1.600 FIGURE 16. SYSTEM TIMIMG DIAGRAM VCC BFLT# EN VOUT PGOOD 1.3V 1.0V VPLL, VSRAM SYSTEM TIMING 2.8V TYP. RISING POR THRESHOLD 2.6V TYP. FALLING POR THRESHOLD SOFT-START SLEW RATE I2C PROGRAMMABLE SLEW RATE Data transferred to the reference DAC on the rising edge of SCL during the ACK bit I2C, SCL ISL6271A |
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Similar Description - ISL6271ACR-T |
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