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RTL8211FD-CG Datasheet(PDF) 50 Page - Realtek Semiconductor Corp. |
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RTL8211FD-CG Datasheet(HTML) 50 Page - Realtek Semiconductor Corp. |
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50 / 72 page  RTL8211F(I)/RTL8211FD(I) Datasheet Integrated 10/100/1000M Ethernet Transceiver 43 Track ID: JATR-8275-15 Rev. 1.1 8.4.20. EPAGSR (Extension Page Select Register, Address 0x1F) Table 41. EPAGSR (Extension Page Select Register, Address 0x1F) Bit Name Type Default Description 31.15:12 RSVD RW 0 Reserved. 31.11:0 ExtPageSel RW 0x000 Page Select (in HEX). 0x000: Page 0 (default page) 8.4.21. PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) Table 42. PC1R (PCS Control 1 Register, MMD Device 3, Address 0x00) Bit Name Type Default Description 3.0.15:11 RSVD RW 0 Reserved. 3.0.10 Clock Stop Enable RW 0 1: PHY stops RXC in LPI 0: RXC not stoppable 3.0.9:0 RSVD RW 0 Reserved. 8.4.22. PS1R (PCS Status1 Register, MMD Device 3, Address 0x01) Table 43. PS1R (PCS Status 1 Register, MMD Device 3, Address 0x01) Bit Name Type Default Description 3.1.15:12 RSVD RO 0 Reserved. 3.1.11 TX LPI Received RO, LH 0 1: TX PCS has received LPI 0: LPI not received 3.1.10 RX LPI Received RO, LH 0 1: RX PCS has received LPI 0: LPI not received 3.19 TX LPI Indication RO 0 1: TX PCS is currently receiving LPI 0: TX PCS is not currently receiving LPI 3.1.8 RX LPI Indication RO 0 1: RX PCS is currently receiving LPI 0: RX PCS is not currently receiving LPI 3.1.7 RSVD RO 0 Reserved. 3.1.6 Clock Stop Capable RO 1 1: MAC stops TXC in LPI 0: TXC not stoppable 3.1.5:0 RSVD RO 0 Reserved. |
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