Integrated 10/100/1000M Ethernet Transceiver
Track ID: JATR-8275-15 Rev. 1.1
7.11. MAC/PHY Interface
The RTL8211F(I)/RTL8211FD(I) supports industry standards and is suitable for most off-the-shelf MACs
with an RGMII interface.
Among the RGMII interface in 100Base-TX and 10Base-T modes, TXC and RXC sources are 25MHz and
2.5MHz respectively; while in 1000Base-T mode, TXC and RXC sources are 125MHz. TXC will always
be generated by the MAC and RXC will always be generated by the PHY. TXD[3:0] and RXD[3:0] signals
are used for data transitions on the rising and falling edge of the clock.
7.11.2. Management Interface
The management interface provides access to the internal registers through the MDC and MDIO pins as
described in IEEE 802.3u section 22. The MDC signal, provided by the MAC, is the management data
clock reference to the MDIO signal. The MDIO is the management data input/output and is a bi-directional
signal that runs synchronously to MDC. The MDIO pin needs a 1.5k Ohm pull-up resistor to maintain the
MDIO high during idle and turnaround.
The RTL8211F(I)/RTL8211FD(I) can share the same MDIO line. In switch/router applications, each port
should be assigned a unique address during the hardware reset sequence, and it can only be addressed via
that unique PHY address. For detailed information on the management registers, see section 8 Register
Descriptions, page 29.
Table 12. Management Frame Format
Management Frame Fields
Table 13. Management Frame Description
32 Contiguous Logical 1’s Sent by the MAC on MDIO, along with 32 Corresponding Cycles on MDC.
This provides synchronization for the PHY.
Start of Frame.
Indicated by a 01 pattern.
Up to eight PHYs can be connected to one MAC. This 3-bit field selects which PHY the frame is directed to.
This is a 5-bit field that sets which of the 32 registers of the PHY this operation refers to.