5504 DCR
Direct Conversion Receiver
4
PIN DESCRIPTIONS
ANALOG PINS
NAME
TYPE
DESCRIPTION
RFP, RFN
I
RF inputs: balanced differential inputs to the receiver. The input signals placed on this
line are amplified with a variable gain amplifier before being passed to the I/Q
demodulator.
AGC
I
Automatic gain control input. A voltage from 0 to 4 volts on this pin varies the input
amplifier gain from minimum to maximum. The gain increase is 25 dB typical
Eon, Filn
I/O
External loop filter interface. Eon drives the base of an external common emitter
transistor. Filn is the feedback input from the loop filter capacitor.
XTLP, XTLN
I
Reference crystal input.
An external crystal connected between these pins
establishes the reference frequency for the PLL synthesizer. Following this oscillator is
a programmable divider that establishes the synthesizer step size.
IO2, QO2
O
Baseband outputs.
These typically drive an A/D converter prior to digital
demodulation and processing.
IO1, QO1
O
I and Q channel outputs to external low pass filter. An external series resistor can be
connected between this output and the filter to provide the source match.
IIN, QIN
I
I and Q channel inputs from external low pass filter. These are high impedance inputs
(>5000
Ω). The low pass filter must be designed for low input and high output
impedance.
Rxt
I
External reference resistor. This resistor is connected to ground and must be 7.68k
±1%. It is used as a reference for internal bias currents.
RSHP, RSHN
I
High range VCO resonator inputs
RSLP, RSLN
I
Low range VCO resonator inputs
DIGITAL PINS
Din
I/O
I2C data. This signal is connected to the I2C internal block. An external resistor
(typically 2.2 kΩ) is connected between Din and Vcc for proper operation
Dclk
I
I2C clock Input. Dclk should nominally be a square wave with a maximum frequency
of 400kHz. SCL is generated by the system I2C master.
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