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RTL8201CP Datasheet(PDF) 9 Page - Realtek Semiconductor Corp.

Part # RTL8201CP
Description  SINGLE-CHIP/SINGLE-PORT 10/100M FAST ETHERNET PHYCEIVER
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8201CP Datasheet(HTML) 9 Page - Realtek Semiconductor Corp.

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RTL8201CP
Datasheet
Single-Chip/Port 10/100 Fast Ethernet PHYceiver
4
Track ID: JATR-1076-21 Rev. 1.1
5.
Pin Description
LI: Latched Input during Power up or Reset
O: Output
I: Input
IO: Bi-directional input and output
P: Power
5.1. MII Interface
Table 1. MII Interface
Name
Type
Pin No.
Description
TXC
O
7
Transmit Clock.
This pin provides a continuous clock as a timing reference for TXD[3:0] and
TXEN.
TXEN
I
2
Transmit Enable.
The input signal indicates the presence of valid nibble data on TXD[3:0].
TXD[3:0]
I
3, 4, 5, 6
Transmit Data.
The MAC will source TXD[0..3] synchronous with TXC when TXEN is
asserted.
RXC
O
16
Receive Clock.
This pin provides a continuous clock reference for RXDV and RXD[0..3]
signals. RXC is 25MHz in 100Mbps mode and 2.5Mhz in 10Mbps mode.
COL
O
1
Collision Detect.
COL is asserted high when a collision is detected on the media.
CRS
O
23
Carrier Sense.
This pin’s signal is asserted high if the media is not in IDEL state.
RXDV
O
22
Receive Data Valid.
This pin’s signal is asserted high when received data is present on the
RXD[3:0] lines. The signal is de-asserted at the end of the packet. The signal is
valid on the rising edge of the RXC.
RXD[3:0]
O
18, 19, 20, 21
Receive Data.
These are the four parallel receive data lines aligned on the nibble boundaries
driven synchronously to the RXC for reception by the external physical unit
(PHY).
RXER/
FXEN
O/LI
24
Receive Error.
If a 5B decode error occurs, such as invalid /J/K/, invalid /T/R/, or invalid
symbol, this pin will go high.
Fiber/UTP Enable.
During power on reset, this pin status is latched to determine the media mode to
operate in.
1: Fiber mode
0: UTP mode
An internal weak pull low resistor, sets this to the default of UTP mode. It is possible
to use an external 5.1K
Ω pull high resistor to enable fiber mode.
After power on, the pin operates as the Receive Error pin.
MDC
I
25
Management Data Clock.
This pin provides a clock synchronous to MDIO, which may be asynchronous
to the transmit TXC and receive RXC clocks. The clock rate can be up to
2.5MHz.
MDIO
IO
26
Management Data Input/Output.
This pin provides the bi-directional signal used to transfer management
information.


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