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PCI2050BIGHK Datasheet(PDF) 6 Page - Texas Instruments |
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PCI2050BIGHK Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 87 page  vi List of Illustrations Figure Title Page 2−1 PCI2050B GHK/ZHK Terminal Diagram 2−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 PCI2050B PDV Terminal Diagram 2−2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 PCI2050B PPM Terminal Diagram 2−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 System Block Diagram 3−1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 PCI AD31−AD0 During Address Phase of a Type 0 Configuration Cycle 3−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 PCI AD31−AD0 During Address Phase of a Type 1 Configuration Cycle 3−4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 Bus Hierarchy and Numbering 3−4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Secondary Clock Block Diagram 3−6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 Clock Mask Read Timing After Reset 3−15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−1 PCI Clock Signal AC Parameter Measurements 6−4 . . . . . . . . . . . . . . . . . . . . 6−3 Load Circuit and Voltage Waveforms 6−6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6−4 RSTIN Timing Waveforms 6−7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . |
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