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CSE7759B Datasheet(PDF) 17 Page - Core Technology (Shenzhen) Co., Ltd.

Part No. CSE7759B
Description  Calibration-free Electric Energy Measuring Chip
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Maker  CHIPSEA [Core Technology (Shenzhen) Co., Ltd.]
Homepage  http://www.chipsea.com/
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本资料为芯海科技专有财产,非经许可,不得复制、翻印或转变其他形式使用。
This document is exclusive property of CHIPSEA and shall not be reproduced or copied or transformed to any other format
without prior permission of CHIPSEA
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Adj.4=0 indicates power cycle of serial port outputted is an incomplete cycle;
Adj.5
Adj.5=1 indicates current cycle of serial port outputted is a complete cycle;
Adj.5=0 indicates current cycle of serial port outputted is an incomplete cycle;
Adj.6
Adj.6=1 indicates voltage cycle of serial port outputted is a complete cycle;
Adj.6=0 indicates voltage cycle of serial port outputted is an incomplete cycle;
Adj.7
Number of pulses is overflowing; Simultaneous Adj.7 inversion
◆Adj0~2: is used to judge calibration data writing address when calibrating. For example
Adj0~2=2, it indicates calibration address is 3D0H~3DFH in this time. The delivery
calibration address is Adj0~2=0- namely, start from 3F0H~ 3FFH.
◆Adj.3: Used to determine whether the coefficient load is correct.
◆Adj.4: When power signal cycle is larger than 1s, present cycle counting time will be
transmitted to the user. This flag bit is used to identify whether the power cycle outputted
at this moment is complete power cycle or power cycle counting larger than 1s.
◆Adj.5: When current signal cycle is larger than 1s, present cycle counting time will be
transmitted to the user. This flag bit is used to identify whether the current cycle
outputted at this moment is complete current cycle or current cycle counting larger than
1s.
◆Adj.6: When voltage signal cycle is larger than 1s, present cycle counting time will be
transmitted to the user. This flag bit is used to identify whether the voltage cycle
outputted at this moment is complete voltage cycle or voltage cycle counting larger than
1s.
◆Adj.7: Number of CF pulses will increase by 1 each time when one pulse signal is
generated at CF pin (pin 7); when accumulated number of CF pulses is overflowing
(overflowing when CFm: CFl=0FFFFH+1), negation will occurs to the value of
calibration coefficient Adj.7 once.
3.5 Chip Reset
After the chip reset, all the data is initialize, that is, the same as the initial power, waiting for
about 550 ms, the serial port output signal starts to sample. How to judge the chip to generate the
reset? When the current cycle value is 0, the initial power or reset of the chip is explained,




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