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H27UCG8T2BTR-BC Datasheet(PDF) 13 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
13
Notes:
1. Random Data Input/Output must be performed in a selected page.
2. Any command between 11h and 81h is prohibited except 70h, 78h, 75h and FFh.
3. Multi-plane Random data-out must be used after multi-plane read operations
(Multi-plane Page Read, Multi-plane Cache Read and Multi-plane Read for Copy Back).
4. Do not change plane address order when using all multi-plane operations.
5. All cache operation (cache program, cache read) is available only within a block.
6. It‟s possible to confirm the multi-plane cache read first step using both 30h and 33h.
Caution:
1. Any undefined command inputs are prohibited except for above command set.
2. Multi-plane page read, multi-plane cache read, and multi-plane read for copy-back must be used
after multi-plane programmed page, multi-plane cache program, and multi-plane copy-back program.
CLE
ALE
CE#
WE#
RE#
WP#
MODE
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input (5 Cycles)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input (5 Cycles)
L
L
L
H
H
Data Input
L
L
L
H
X
Sequential Read and Data Output
X
X
X
H
H
X
During Read (Busy)
X
X
X
X
X
H
During Program (Busy)
X
X
X
X
X
H
During Erase (Busy)
X
X
X
X
X
L
Write Protect
X
X
H
X
X
0V/Vcc
Stand-By
Notes:
1. X can be VIL or VIH. H = Logic level “High”. L = Logic level “Low”.
2. WP# should be biased to CMOS high or CMOS low for stand-by mode.
3. WE# and RE# during Read Busy must be keep on high to prevent unplanned
command/address/data input or to avert unintended data out. In this time, only Reset,
Read Status, and Multi-plane Read Status can be inputted to the device.
1)
1)
1)
3)
3)
2)
1.10. Mode Selection




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