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H27UCG8T2BTR-BC Datasheet(HTML) 41 Page - Hynix Semiconductor

Part No. H27UCG8T2BTR-BC
Description  64Gb(8192M x 8bit) MLC NAND Flash
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Maker  HYNIX [Hynix Semiconductor]
Homepage  http://www.skhynix.com/ko/index.jsp
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H27UCG8T2BTR-BC Datasheet(HTML) 41 Page - Hynix Semiconductor

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H27UCG8T2BTR-BC
64Gb(8192M x 8bit) MLC NAND Flash
Rev 0.1 / Oct. 2012
41
Figure 36 : Multi plane cache read
Notes:
1. plane 0 and plane 1 should be selected within the same chip
2. Only one block should be selected from the each plane.
3. Multi plane cache read is available only within a block per plane.
4. Selected Page address except A23 within two blocks must be same.
5. The operation has to be terminated with “3Fh” command.
6. It‟s possible to confirm the multi-plane cache read first step using both 30h and 33h.
4.5. Multi Plane Cache Read (available only within a block)
The device supports multi-plane cache read, which enables high read throughput by reading two pages in
parallel. Figure 36 shows the command sequence for the multi-plane cache read operation. Both confirm
commands, 30h and 33h, are valid for the first page read sequence.
4.6. Multi Plane Cache Read Enhanced (available only within a block)
This command is a multi-plane extension of the Cache Read Enhanced command.


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