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RF96 Datasheet(PDF) 92 Page - HOPE Microelectronics CO., Ltd. |
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RF96 Datasheet(HTML) 92 Page - HOPE Microelectronics CO., Ltd. |
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92 / 121 page  Page 92 RF96/97/98 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com WIRELESS & SENSING PRELIMINARY DATASHEET Name (Address) Bits Variable Name Mode Default value FSK/OOK Description RegAfcFei (0x1a) 7-5 unused r - unused 4 AgcStart wt 0x00 Triggers an AGC sequence when set to 1. 3 reserved rw 0x00 reserved 2 unused - - unused 1 AfcClear wc 0x00 Clear AFC register set in Rx mode. Always reads 0. 0 AfcAutoClearOn rw 0x00 Only valid if AfcAutoOn is set 0 AFC register is not cleared at the beginning of the automatic AFC phase 1 AFC register is cleared at the beginning of the automatic AFC phase RegAfcMsb (0x1b) 7-0 AfcValue(15:8) rw 0x00 MSB of the AfcValue, 2 ‟s complement format. Can be used to overwrite the current AFC value RegAfcLsb (0x1c) 7-0 AfcValue(7:0) rw 0x00 LSB of the AfcValue, 2 ‟s complement format. Can be used to overwrite the current AFC value RegFeiMsb (0x1d) 7-0 FeiValue(15:8) rw - MSB of the measured frequency offset, 2 ‟s complement. Must be read before RegFeiLsb. RegFeiLsb (0x1e) 7-0 FeiValue(7:0) rw - LSB of the measured frequency offset, 2 ‟s complement Frequency error = FeiValue x Fstep RegPreambleDetect (0x1f) 7 PreambleDetectorOn rw 0x01 * Enables Preamble detector when set to 1. The AGC settings supersede this bit during the startup / AGC phase. 0 Turned off 1 Turned on 6-5 PreambleDetectorSize rw 0x01 * Number of Preamble bytes to detect to trigger an interrupt 00 1 byte 10 3 bytes 01 2 bytes 11 Reserved 4-0 PreambleDetectorTol rw 0x0A * Number or chip errors tolerated over PreambleDetectorSize. 4 chips per bit. RegRxTimeout1 (0x20) 7-0 TimeoutRxRssi rw 0x00 Timeout interrupt is generated TimeoutRxRssi*16*Tbit after switching to Rx mode if Rssi interrupt do esn‟t occur (i.e. RssiValue > RssiThreshold) 0x00: TimeoutRxRssi is disabled RegRxTimeout2 (0x21) 7-0 TimeoutRxPreamble rw 0x00 Timeout interrupt is generated TimeoutRxPreamble*16*Tbit after switching to Rx mode if Preamble interrupt do esn‟t occur 0x00: TimeoutRxPreamble is disabled RegRxTimeout3 (0x22) 7-0 TimeoutSignalSync rw 0x00 Timeout interrupt is generated TimeoutSignalSync*16*Tbit after the Rx mode is programmed, if SyncAddress do esn‟t occur 0x00: TimeoutSignalSync is disabled RegRxDelay (0x23) 7-0 InterPacketRxDelay rw 0x00 Additional delay before an automatic receiver restart is launched: Delay = InterPacketRxDelay*4*Tbit RC Oscillator registers |
Similar Part No. - RF96 |
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Similar Description - RF96 |
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