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RF96 Datasheet(PDF) 46 Page - HOPE Microelectronics CO., Ltd. |
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RF96 Datasheet(HTML) 46 Page - HOPE Microelectronics CO., Ltd. |
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46 / 121 page  Page 46 RF96/97/98 Tel: +86-755-82973805 Fax: +86-755-82973550 E-mail: sales@hoperf.com http://www.hoperf.com WIRELESS & SENSING PRELIMINARY DATASHEET Alternative OOK Demodulator Threshold Modes In addition to the Peak OOK threshold mode, the user can alternatively select two other types of threshold detectors: Fixed Threshold: The value is selected through OokFixedThresh Average Threshold: Data supplied by the RSSI block is averaged, and this operation mode should only be used with DC-free encoded data. 4.2.3.3. Bit Synchronizer The bit synchronizer provides a clean and synchronized digital output based upon timing recovery information gleaned from the received data edge transitions. Its output is made available on pin DIO1/DCLK in Continuous mode and can be disabled through register settings. However, for optimum receiver performance, especially in Continuous receive mode, its use is strongly advised. The Bit Synchronizer is automatically activated in Packet mode. Its bit rate is controlled by BitRateMsb and BitRateLsb in RegBitrate. Raw demodulator output (FSK or OOK) BitSync Output To pin DATA and DCLK in continuous mode DATA DCLK Figure 15. Bit Synchronizer Description To ensure correct operation of the Bit Synchronizer, the following conditions have to be satisfied: A preamble (0x55 or 0xAA) of at least 12 bits is required for synchronization, the longer the synchronization phase is the better the ensuing packet detection rate will be. The subsequent payload bit stream must have at least one edge transition (either rising or falling) every 16 bits during data transmission. The absolute error between transmitted and received bit rate must not exceed 6.5%. |
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Similar Description - RF96 |
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