Everest Semiconductor
ES8155
Version 1.0
3/29/2011
10
5.2
2-wire
2-wire interface is a bi-directional serial bus that uses a serial data line (SDA)
and a serial clock line (SCL) for data transfer. The timing diagram for data
transfer of this interface is given in Figure 2. Data are transmitted
synchronously to SCL clock on the SDA line on a byte-by-byte basis. Each bit
in a byte is sampled during SCL high with MSB bit being transmitted firstly.
Each transferred byte is followed by an acknowledge bit from receiver to pull
the SDA low. The transfer rate of this interface can be up to 100k bps.
A master controller initiates the transmission by sending a “start” signal, which
is defined as a high-to-low transition at SDA while SCL is high. The first byte
transferred is the slave address. It is a seven-bit chip address followed by a
RW bit. The chip address must be 001000x,where x equals AD0 (pin CE). The
RW bit indicates the slave data transfer direction. Once an acknowledge bit is
received, the data transfer starts to proceed on a byte-by-byte basis in the
direction specified by the RW bit. The master can terminate the communication
by generating a “stop” signal, which is defined as a low-to-high transition at
SDA while SCL is high.
In 2-wire interface mode, the registers can be written and read. The formats of
“write” and “read” instructions are shown in Table 3 and Table 4. Please note
that, to read data from a register, you must set R/W bit to 0 to access the
register address and then set R/W to 1 to read data from the register. There
are no acknowledge bit after data to be written or read, this is the only
difference from the I
2C protocol.
Table 3 Write Data to Register in 2-wire Interface Mode
Chip Address
R/W
Register Address
Data to be written
001000
AD0
0
ACK
RAM
ACK
DATA
Table 4 Read Data from Register in 2-wire Interface Mode
Chip Address
R/W
Register Address
001000
AD0
0
ACK
RAM
Chip Address
R/W
Data to be read
001000
AD0
1
ACK
DATA
Figure 2 Complete Data Transfer for 2-wire Interface
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