ADVANCED INFORMATION
DESCRIPTION:
The M-Densus series is a family of interchangeable memory modules. The 256 Megabit SDRAM is a member of
this family which utilizes the new and innovative space saving TSOP stacking technology. The modules are
constructed with 8 Meg x 16 SDRAMs.
This 128 Megabit based M-Densus module, the
DPSD16MX16TY5 has been designed to fit in the same
footprint as the 8 Meg x 16 SDRAM TSOP monolithic and
128 Megabit SDRAM based family of M-Densus modules.
This allows the memory board designer to upgrade the
memory in their products without redesigning the
memory board, thus saving time and money.
FEATURES:
• Configuration Available:
16 Meg x 16 bit (with two Chip Selects)
• Clock Frequency:
66[1], 83[1], 100, 125[2], 133[2] MHz (max.)
• PC100 and PC133 Compatible
• 3.3V Supply
• LVTTL Compatible I/O
• Four Bank Operation
• Programmable Burst Type, Burst Length,
and CAS Latency
• 4096 Cycles / 64 ms
• Auto and Self Refresh
• Package: TSOP Leadless Stack
NOTES: [1] Available in Industrial Temperature Ranges Only.
[2] Available in Commercial Temperature Range Only.
PIN-OUT DIAGRAM
FUNCTIONAL BLOCK DIAGRAM
16Mx16, 7.5 - 15ns, P12, M-Densus
30A232-00
A
This document contains information on a product under consideration for
development at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right
to change or discontinue information on this product without prior notice.
PIN NAMES
A0 - A11
Row Address:
A0 - A11
Column Address: A0 - A8
BA0, BA1
Bank Select Address
DQ0 - DQ15
Data In / Data Out
CAS
Column Address Strobes
RAS
Row Address Enables
WE
Data Write Enable
UDQM,
LDQM
Upper & Lower
Data Input/Output Mask
CKE
Clock Enable
CLK
System Clock
CS0-CS1
Chip Selects
VCC/VSS
Power Supply/Ground
VCCQ/VSSQ
Data Output Power/Ground
N.C./RFU
No Connect
Reserved for Future Use
256 Megabit Synchronous DRAM
DPSD16MX16TY5
M-Densus
High Density Memory Device
30A232-00
REV. A
1
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