RTL8100B datasheet(38/66 Pages) REALTEK

Part #	RTL8100B

Description	SINGLE-CHIP 10/100MBPS ETHERNET CONTROLLER WITH POWER MANAGEMENT

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Manufacturer	REALTEK [Realtek Semiconductor Corp.]

Direct Link	https://www.realtek.com/en/

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RTL8100B(L)

Datasheet

Single-Chip 10/100 Ethernet Controller w/Power Management

32

Track ID: JATR-1076-21 Rev. 1.5

Bytes

Contents

Description

Bit7-3: Reserved.

Bit2: Link Down Power Saving mode:

Set to 1: Disable.

Set to 0: Enable. When cable is disconnected(Link Down), the analog part will power

down itself (PHY Tx part & part of twister) automatically except PHY Rx part and

part of twister to monitor SD signal in case that cable is re-connected and Link should

be established again.

Bit1: LANWake signal Enable/Disable

Set to 1: Enable LANWake signal.

Set to 0: Disable LANWake signal.

Bit0: PME_Status bit property

Set to 1: The PME_Status bit can be reset by PCI reset or by software if

D3cold_support_PME is 0. If D3cold_support_PME=1, the PME_Status bit is a

sticky bit.

Set to 0: The PME_Status bit is always a sticky bit and can only be reset by software.

20h-23h

TW_PARM_U

Reserved. Do not change this filed without Realtek approval.

Twister Parameter U for RTL8100B(L). Operational registers of the RTL8100B(L) are

7Ch-7Fh.

24h-27h

TW_PARM_T

Reserved. Do not change this filed without Realtek approval.

Twister Parameter T for RTL8100B(L). Operational registers of the RTL8100B(L) are

7Ch-7Fh.

28h-2Bh

PHY1_PARM_T

Reserved. Do not change this filed without Realtek approval.

PHY Parameter 1-T for RTL8100B(L). Operational registers of the RTL8100B(L) are

from 78h to 7Bh.

2Ch

PHY2_PARM_T

Reserved. Do not change this filed without Realtek approval.

PHY Parameter 2-T for RTL8100B(L). Operational register of the RTL8100B(L) is 80h.

2Dh-31h

-

Reserved.

32h-33h

CheckSum

Reserved. Do not change this filed without Realtek approval.

Checksum of the EEPROM content.

34h-3Eh

-

Reserved. Do not change this filed without Realtek approval.

3Fh

PXE_Para

Reserved. Do not change this filed without Realtek approval.

PXE ROM code parameter.

40h-7Fh

VPD_Data

VPD data filed. Offset 40h is the start address of the VPD data.

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RTL8100B Datasheet(PDF) 38 Page - Realtek Semiconductor Corp.

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