RTL8100BL datasheet(43/66 Pages) REALTEK

Part #	RTL8100BL

Description	SINGLE-CHIP 10/100MBPS ETHERNET CONTROLLER WITH POWER MANAGEMENT

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Manufacturer	REALTEK [Realtek Semiconductor Corp.]

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RTL8100B(L)

Datasheet

Single-Chip 10/100 Ethernet Controller w/Power Management

37

Track ID: JATR-1076-21 Rev. 1.5

RID: Revision ID Register

The Revision ID register is an 8-bit register that specifies the RTL8100B(L) controller revision number.

PIFR: Programming Interface Register

The programming interface register is an 8-bit register that identifies the programming interface of the RTL8100B(L)

controller. Because the PCI version 2.1 specification does not define any specific value for network devices, PIFR = 00h.

SCR: Sub-Class Register

The Sub-class register is an 8-bit register that identifies the function of the RTL8100B(L). SCR = 00h indicates that the

RTL8100B(L) is an Ethernet controller.

BCR: Base-Class Register

The Base-class register is an 8-bit register that broadly classifies the function of the RTL8100B(L). BCR = 02h indicates

that the RTL8100B(L) is a network controller.

CLS: Cache Line Size

Reads will return a 0, writes are ignored.

LTR: Latency Timer Register

Specifies, in units of PCI bus clocks, the value of the latency timer of the RTL8100B(L).

When the RTL8100B(L) asserts FRAMEB, it enables its latency timer to count. If the RTL8100B(L)

deasserts FRAMEB prior to count expiration, the content of the latency timer is ignored. Otherwise,

after the count expires, the RTL8100B(L) initiates transaction termination as soon as its GNTB is

deasserted. Software is able to read or write, and the default value is 00H.

HTR: Header Type Register

Reads will return a 0, writes are ignored.

BIST: Built-in Self Test

Reads will return a 0, writes are ignored.

IOAR: This register specifies the BASE IO address which is required to build an address map during configuration. It also

specifies the number of bytes required as well as an indication that it can be mapped into IO space.

Bit

Symbol

Description

31-8

IOAR31-8 BASE IO Address: This is set by software to the Base IO address for the operational register map.

7-2

IOSIZE

Size Indication: Read back as 0. This allows the PCI bridge to determine that the RTL8100B(L)

requires 256 bytes of IO space.

1

-

Reserved

0

IOIN

IO Space Indicator: Read only. Set to 1 by the RTL8100B(L) to indicate that it is capable of being

mapped into IO space.

MEMAR: This register specifies the base memory address for memory accesses to the RTL8100B(L) operational registers. This

register must be initialized prior to accessing any RTL8100B(L)'s register with memory access.

Bit

Symbol

Description

31-8

MEM31-8 Base Memory Address: This is set by software to the base address for the operational register map.

7-4

MEMSIZE Memory Size: These bits return 0, which indicates that the RTL8100B(L) requires 256 bytes of

Memory Space.

3

MEMPF

Memory Prefetchable: Read only. Set to 0 by the RTL8100B(L).

2-1

MEMLOC Memory Location Select: Read only. Set to 0 by the RTL8100B(L). This indicates that the base

register is 32-bit wide and can be placed anywhere in the 32-bit memory space.

0

MEMIN

Memory Space Indicator: Read only. Set to 0 by the RTL8100B(L) to indicate that it is capable of

being mapped into memory space.

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