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RTL8101E-GR Datasheet(PDF) 25 Page - Realtek Semiconductor Corp.

Part # RTL8101E-GR
Description  INTEGRATED FAST ETHERNET CONTROLLER FOR PCI EXPRESS??APPLICATIONS
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Manufacturer  REALTEK [Realtek Semiconductor Corp.]
Direct Link  https://www.realtek.com/en/
Logo REALTEK - Realtek Semiconductor Corp.

RTL8101E-GR Datasheet(HTML) 25 Page - Realtek Semiconductor Corp.

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RTL8101E-GR
Datasheet
Integrated Fast Ethernet Controller for PCI Express
20
Track ID: JATR-1076-21
Rev. 1.1
7.7.2.
Differential Receiver Parameters
Table 18. Differential Receiver Parameters
Symbol
Parameter
Min.
Typical
Max.
Units
UI
Unit Interval
399.88
400
400.12
ps
VRX-DIFFp-p
Differential Input Peak to Peak Voltage
0.175
1.200
V
TRX-EYE
Minimum Receiver Eye Width
0.4
UI
TRX-EYE-MEDIAN-to-
MAX-JITTER
Maximum time between the jitter median and
maximum deviation from the median
0.3
UI
VRX-CM-ACp
AC Peak Common Mode Input Voltage
150
mV
RLRX-DIFF
Differential Return Loss
15
dB
RLRX-CM
Common Mode Return Loss
6
dB
ZRX-DIFF-DC
DC Differential Input Impedance
80
100
120
ZRX--DC
DC Input Impedance
40
50
60
ZRX-HIGH-IMP-DC
Powered Down DC Input Impedance
200 k
VRX-IDLE-DET-DIFFp-p Electrical Idle Detect Threshold
65
175
mV
TRX-IDLE-DET-
DIFFENTERTIME
Unexpected Electrical Idle Enter Detect Threshold
Integration Time
10
ms
LRX-SKEW
Total Skew
20
ns
Note: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each parameter.
7.7.3.
REFCLK Parameters
Table 19. REFCLK Parameters
Symbol
Parameter
100MHz Input
Min
Max
Units
Tabsmin
Absolute min. DIF CLK Period
9.872
ns
Trise
Rise Time
175
700
ps
Tfall
Fall Time
175
700
ps
h∆ Trise
Rise Time Variation
125
ps
∆ Tfall
Fall Time Variation
125
ps
Rise/Fall Matching
20
%
Vhigh
Voltage High (typical 0.71V)
660
850
mV
Vlow
Voltage Low (typical 0.0V)
-150
mV
Vcross absolute
Absolute Crossing Point Voltages
250
550
mV
Vcross relative
Relative Crossing Point Voltages
Note2
Note2
V
Total ∆ Vcross
Total Variation of Vcross over all edges
140
mV
Tccjitter
Cycle to Cycle Jitter
125
ps
Duty Cycle
45
55
%
Vovs
Maximum Voltage (Overshoot)
Vhigh_avg + 0.3
V
Vuds
Minimum Voltage (Undershoot)
-0.3
V
Vrb
Ringback Voltage
0.2
N/A
V
Note1: Refer to PCI Express Base Specification, rev.1.0a, for correct measurement environment setting of each
parameter.
Note2: Vcross relative Min = 0.5(Vhigh_avg – 0.710) + 0.250, Vcross relative Max = 0.5(Vhigh_avg – 0.710) + 0.550.
The crossing point must meet the absolute and relative crossing point specifications simultaneously.
Note3: The nominal single-ended swing for each clock is 0 to 0.7V with a nominal frequency of 100MHz ±300 PPM.
Note4: The reference clocks may support spread spectrum clocking. The minimum clock period cannot be violated.


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