RTL8100B-GR datasheet(36/66 Pages) REALTEK

Part #	RTL8100B-GR

Description	SINGLE-CHIP 10/100MBPS ETHERNET CONTROLLER WITH POWER MANAGEMENT

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Manufacturer	REALTEK [Realtek Semiconductor Corp.]

Direct Link	https://www.realtek.com/en/

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RTL8100B(L)

Datasheet

Single-Chip 10/100 Ethernet Controller w/Power Management

30

Track ID: JATR-1076-21 Rev. 1.5

6.28. Config5: Configuration Register 5

(Offset 00D8h, R/W)

This register, unlike other Config registers, is not protected by 93C46 Command register. I.e. there is no

need to enable Config register write prior to writing to Config5.

Bit

R/W

Symbol

Description

7

-

Reserved

6

R/W

BWF

Broadcast Wakeup Frame:

1: Enable Broadcast Wakeup Frame with mask bytes of only DID

field = FF FF FF FF FF FF.

0: Default value. Disable Broadcast Wakeup Frame with mask bytes

of only DID field = FF FF FF FF FF FF.

The power-on default value of this bit is 0.

5

R/W

MWF

Multicast Wakeup Frame:

1: Enable Multicast Wakeup Frame with mask bytes of only DID

field, which is a multicast address.

0: Default value. Disable Multicast Wakeup Frame with mask bytes

of only DID field, which is a multicast address.

The power-on default value of this bit is 0.

4

R/W

UWF

Unicast Wakeup Frame:

1: Enable Unicast Wakeup Frame with mask bytes of only DID

field, which is its own physical address.

0: Default value. Disable Unicast Wakeup Frame with mask bytes of

only DID field, which is its own physical address.

The power-on default value of this bit is 0.

3

R/W

FIFOAddrPtr

FIFO Address Pointer: (Realtek internal use only to test FIFO SRAM)

1: Both Rx and Tx FIFO address pointers are updated in descending

way from 1FFh and downwards. The initial FIFO address pointer is

1FFh.

0: (Power-on) default value. Both Rx and Tx FIFO address pointers

are updated in ascending way from 0 and upwards. The initial FIFO

address pointer is 0.

Note: This bit does not participate in EEPROM auto-load. The FIFO

address pointers can not be reset, except initial power-on.

The power-on default value of this bit is 0.

2

R/W

LDPS

Link Down Power Saving mode:

1: Disable.

0: Enable. When cable is disconnected (Link Down), the analog part

will power down itself (PHY Tx part & part of twister) automatically

except PHY Rx part and part of twister to monitor SD signal in case

that cable is re-connected and Link should be established again.

1

R/W

LANWake

LANWake signal enable/disable:

1: Enable LANWake signal.

0: Disable LANWake signal.

0

R/W

PME_STS

PME_Status bit: Always sticky/can be reset by PCI RST# and

software.

1: The PME_Status bit can be reset by PCI reset or by software.

0: The PME_Status bit can only be reset by software.

Config5 register, offset D8h: (SYM_ERR register is changed to Config5, the function of SYM_ERR register is no longer

supported by RTL8100B(L).)

The 3 bits (bit2-0) are auto-loaded from EEPROM Config5 byte to RTL8100B(L) Config5 register.

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RTL8100B-GR Datasheet(PDF) 36 Page - Realtek Semiconductor Corp.

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