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RTL8100BL-GR Datasheet(PDF) 44 Page - Realtek Semiconductor Corp. |
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RTL8100BL-GR Datasheet(HTML) 44 Page - Realtek Semiconductor Corp. |
44 / 66 page RTL8100B(L) Datasheet Single-Chip 10/100 Ethernet Controller w/Power Management 38 Track ID: JATR-1076-21 Rev. 1.5 SVID: Subsystem Vendor ID. This field will be set to a value corresponding to PCI Subsystem Vendor ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 10ECh which is Realtek Semiconductor's PCI Subsystem Vendor ID. SMID: Subsystem ID. This field will be set to value corresponding to PCI Subsystem ID in the external EEPROM. If there is no EEPROM, this field will default to a value of 8139h. ILR: Interrupt Line Register The Interrupt Line Register is an 8-bit register used to communicate with the routing of the interrupt. It is written by the POST software to set interrupt line for the RTL8100B(L). IPR: Interrupt Pin Register The Interrupt Pin register is an 8-bit register indicating the interrupt pin used by the RTL8100B(L). The RTL8100B(L) uses INTA interrupt pin. Read only. IPR = 01H. MNGNT: Minimum Grant Timer: Read only Specifies how long a burst period the RTL8100B(L) needs at 33 MHz clock rate in units of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. MXLAT: Maximum Latency Timer: Read only Specifies how often the RTL8100B(L) needs to gain access to the PCI bus in unit of 1/4 microsecond. This field will be set to a value from the external EEPROM. If there is no EEPROM, this field will default to a value of 20h. |
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