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RTL8110S-32 Datasheet(PDF) 23 Page - Realtek Semiconductor Corp. |
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RTL8110S-32 Datasheet(HTML) 23 Page - Realtek Semiconductor Corp. |
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23 / 43 page  RTL8110S-32 Datasheet Integrated Gigabit Ethernet Controller (LOM) 17 Track ID: JATR-1076-21 Rev. 1.8 6.6. EEPROM Interface The RTL8110S supports the attachment of an external EEPROM. The 93C46 is a 1K-bit EEPROM (the 93C56 is a 2K-bit EEPROM). The EEPROM interface provides the ability for the RTL8110S to read from and write data to an external serial EEPROM device. Values in the external EEPROM allow default fields in PCI configuration space and I/O space to be overridden following a reboot or software EEPROM auto load command. The RTL8110S will auto load values from the EEPROM. If the EEPROM is not present, the RTL8110S initialization uses default values for the appropriate Configuration and Operational Registers. Software can read and write to the EEPROM using ‘bit-bang’ accesses via the 9346CR Register. The interface consists of EESK, EECS, EEDO, and EEDI. Table 10. EEPROM Interface EEPROM Description EECS 93C46 (93C56) chip select. EESK EEPROM serial data clock. EEDI/Aux Input data bus/Input pin to detect if Aux. Power exists or not on initial power-on. This pin should be connected to Boot PROM. To support wakeup from ACPI D3cold or APM power-down, this pin must be pulled high to aux. power via a resistor. If this pin is not pulled high to Aux. Power, the RTL8110S assumes that no Aux. Power exists. EEDO Output data bus. 6.7. Power Management The RTL8110S is compliant with ACPI (Rev 1.0, 1.0b, 2.0), PCI Power Management (Rev 1.1), and Network Device Class Power Management Reference Specification (V1.0a), such as to support an OS-directed Power Management (OSPM) environment. The RTL8110S can monitor the network for a Wakeup Frame, a Magic Packet, or a Re-LinkOk, and notify the system via PME# when such a packet or event occurs. Then, the whole system can be restored to a normal state to process incoming jobs. |
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