©2004 Fairchild Semiconductor Corporation

RMLA3565C Rev. C

Figure 3. Schematic for a Typical Test Evaluation Board (RMLA3565C-TB)

Figure 4. Layout and Assembly of Test Evaluation Board (RMLA3565C-TB)

RF Out

J2

U1

RF In

J1

C1 & C2

(OPT)

C3

GROUND

(GND) P2

Vdd P1

Pin 5 must be grounded

Fairchild

Test Procedure for the evaluation board (RMLA3565C-TB)

The following sequence of procedure must be followed to

properly test the power amplifier:

Step 1: Turn off RF input power.

Step 2: Use GND terminal of the evaluation board to

connect DC supply grounds and Pin 5.

Step 3: Apply drain supply voltage of +4.0V to evaluation

board terminal Vdd.

Step 4: After the bias condition is established, RF input

signal may now be applied.

Step 5: Follow turn-off sequence of:

(i) Turn off RF input power.

(ii) Turn down and off Vdd.

C1

(OPT)

C2

(OPT)

C3

RF In

J1

RF Out

J2

RMLA3565C-58

GND

P2

Vdd

P1