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W79E633A Datasheet(PDF) 31 Page - Nuvoton Technology Corporation |
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W79E633A Datasheet(HTML) 31 Page - Nuvoton Technology Corporation |
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31 / 117 page  W79E633A/W79L633A Publication Release Date: Oct 07, 2010 - 31 - Revision A6.0 TF2 EXF2 RCLK TCLK EXEN2 TR2 2 T C / 2 RL CP / Mnemonic: T2CON Address: C8h BIT NAME FUNCTION 7 TF2 Timer 2 Overflow flag: This bit is set when Timer 2 overflows. It is also set when the count is equal to the capture register in down-count mode. It can be set by the hardware only if RCLK and TCLK are both 0, and it can be set or cleared by software. 6 EXF2 Timer 2 External flag: A negative transition on the T2EX pin (P1.1) or a timer 2 underflow / overflow sets this flag according to the CP/RL2, EXEN2 and DCEN bits. This bit can also be set by the software. If set by a negative transition, this flag must be cleared by software. If set by a negative transition or by software, a Timer 2 interrupt is generated, if enabled. 5 RCLK Receive Clock flag: This bit determines the serial-port time base when receiving data in Serial Port modes 1 or 3. 0: The Timer 1 overflow is used for baud-rate generation 1: The Timer 2 overflow is used for baud-rate generation, forcing Timer 2 into baud- rate generator mode. 4 TCLK Transmit Clock flag: This bit determines the serial-port time base when transmitting data in Serial Port modes 1 or 3. 0: The Timer 1 overflow is used for baud-rate generation 1: The Timer 2 overflow is used for baud-rate generation, forcing Timer 2 into baud- rate generator mode. 3 EXEN2 Timer 2 External Enable: This bit enables the capture / reload function on the T2EX pin, as long as Timer 2 is not generating baud clocks for the serial port. 0: Ignore T2EX. 1: Negative transitions on T2EX result in capture or reload. 2 TR2 Timer 2 Run Control: This bit enables / disables Timer 2. When disabled, Timer 2 preserves the current values in TH2 and TL2. 1 T2 C/ Counter / Timer select: 0: Timer 2 operates as a timer at a speed depending on T2M bit (CKCON.5) 1: Timer 2 counts negative edges on the T2EX pin. Regardless of this bit, Timer 2 may be forced into baud-rate generator mode. 0 RL2 CP/ Capture / Reload select, when Timer 2 overflows or when a falling edge is detected on T2EX (and EXEN2 = 1). 0: Auto-reload Timer 2 1: Capture in Timer 2 If RCLK or TCLK is set, this bit does not function, and Timer 2 runs in auto-reload mode following each overflow. TIMER 2 MODE CONTROL Bit: 7 6 5 4 3 2 1 0 |
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