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W79E659A40FL Datasheet(PDF) 69 Page - Nuvoton Technology Corporation |
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W79E659A40FL Datasheet(HTML) 69 Page - Nuvoton Technology Corporation |
69 / 115 page W79E659A/W79L659A Publication Release Date: Oct 08, 2010 - 69 - Revision A5.0 255 PWMn PWM Cycle PWM Cycle Figure 13-2 PWM Duty Ratio If register PWMn is loaded with a new value, the associated output is updated immediately. By loading PWMn with 00H or FFH, the corresponding channel provides a constant high or low level output, respectively. Since the 8-bit counter counts modulo 255, it can never actually reach FFh, so the output remains low all the time. Buffered PWM outputs may be used to drive DC motors. In this case, the rotation speed of the motor is proportional to the contents of PWMn. The repetition frequency Fpwm for channel n is given by: 255 PWMP) (1 2 Fosc Fpwm × + × = Prescale division factor = PWM + 1 PWMn high/low ratio of (PWMn) - 255 (PWMn) PWMn = This gives a repetition frequency range of 123 Hz to 31.4 KHz ( osc f = 16 MHz). Please refer as below code. mov pwmcon1, #00110011b ; enable pwm3, 2, 1, 0 mov pwmp, #40h ; Fpwm = Fosc/(2*(1+PWMP)*255) mov pwm0, #14h ; duty cycle high/low = PWM0/(255-PWM0) mov pwm1, #18h mov pwm2, #20h mov pwm3, #b0h mov pwmcon1, #11111111b ; output enable pwm3, 2, 1, 0 |
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