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W79E659A40FL Datasheet(PDF) 79 Page - Nuvoton Technology Corporation |
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W79E659A40FL Datasheet(HTML) 79 Page - Nuvoton Technology Corporation |
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79 / 115 page  W79E659A/W79L659A Publication Release Date: Oct 08, 2010 - 79 - Revision A5.0 15.1.5 I2C Clock Baud Rate Control, I2CLKx The data baud rate of I2C is determined by I2CLKx register when I2C port is in a master mode. In the slave modes, SIO1 will automatically synchronize with any clock frequency up to 400 KHz from master I2C device. The data baud rate of I2C setting conforms to the following equation. Data Baud Rate of I2C = FCPU / ( I2CLKx + 1), where FCPU = FOSC/4 . For example, if FOSC=16MHz (FCPU=4MHz), the I2CLK=40(28H), the baud rate =4MHz/(40+1) = 97.56K bits/sec. 15.1.6 I2C Time-out Counter, I2Timerx In W79E659, the I2C logic block provides a 14-bit timer-out counter that helps user to deal with bus pending problem. When SI is cleared user can set ENTI=1 to start the time-out counter. If I2C bus hangs up too long to get any valid signal from devices on the bus, the time-out counter overflows cause TIF=1 to request an I2C interrupt. The I2C interrupt is requested in the condition of either SI=1 or TIF=1. Flags SI and TIF must be cleared by software. Figure 15-3 I2C Time-out Counter 15.2 Modes of Operation The on-chip I2C ports support four operation modes, Master transmitter, Master receiver, Slave transmitter and Slave receiver. In a given application, I2C port may operate as a master and as a slave. In the slave mode, the I2C port hardware looks for its own slave address and the general call address. If one of these addresses is detected, an interrupt is requested. When the microcontroller wishes to become the bus master, the hardware waits until the bus is free before the master mode is entered so that a possible slave action is not interrupted. If bus arbitration is lost in the master mode, I2C port switches to the slave mode immediately and can detect its own slave address in the same serial transfer. 15.2.1 Master Transmitter Mode Serial data output through SDAx while SCLx outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the data direction bit. In this case the data direction bit (R/W) will be logic 0, and we say that a “W” is transmitted. Thus the first byte transmitted is SLA+W. Serial data is transmitted 8 bits at a time. After each byte is transmitted, an |
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