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ICM-20608-G Datasheet(PDF) 27 Page - TDK Electronics |
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ICM-20608-G Datasheet(HTML) 27 Page - TDK Electronics |
27 / 35 page ICM-20608-G Page 27 of 35 Document Number: DS-000081 Revision: 1.0 To write the internal ICM-20608-G registers, the master transmits the start condition (S), followed by the I 2C address and the write bit (0). At the 9 th clock cycle (when the clock is high), the ICM-20608-G acknowledges the transfer. Then the master puts the register address (RA) on the bus. After the ICM-20608-G acknowledges the reception of the register address, the master puts the register data onto the bus. This is followed by the ACK signal, and data transfer may be concluded by the stop condition (P). To write multiple bytes after the last ACK signal, the master can continue outputting data rather than transmitting a stop signal. In this case, the ICM- 20608-G automatically increments the register address and loads the data to the appropriate register. The following figures show single and two-byte write sequences. Single-Byte Write Sequence Burst Write Sequence To read the internal ICM-20608-G registers, the master sends a start condition, followed by the I 2C address and a write bit, and then the register address that is going to be read. Upon receiving the ACK signal from the ICM-20608-G, the master transmits a start signal followed by the slave address and read bit. As a result, the ICM-20608-G sends an ACK signal and the data. The communication ends with a not acknowledge (NACK) signal and a stop bit from master. The NACK condition is defined such that the SDA line remains high at the 9 th clock cycle. The following figures show single and two-byte read sequences. Single-Byte Read Sequence Burst Read Sequence 6.4 I 2C TERMS SIGNAL DESCRIPTION S Start Condition: SDA goes from high to low while SCL is high AD Slave I 2C address W Write bit (0) R Read bit (1) ACK Acknowledge: SDA line is low while the SCL line is high at the 9 th clock cycle NACK Not-Acknowledge: SDA line stays high at the 9 th clock cycle RA ICM-20608-G internal register address DATA Transmit or received data P Stop condition: SDA going from low to high while SCL is high Table 15. I 2C Terms Master S AD+W RA DATA P Slave ACK ACK ACK Master S AD+W RA DATA DATA P Slave ACK ACK ACK ACK Master S AD+W RA S AD+R NACK P Slave ACK ACK ACK DATA Master S AD+W RA S AD+R ACK NACK P Slave ACK ACK ACK DATA DATA |
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