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MB81ES171625 Datasheet(PDF) 9 Page - Fujitsu Component Limited. |
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MB81ES171625 Datasheet(HTML) 9 Page - Fujitsu Component Limited. |
9 / 43 page MB81ES171625/173225-15-X 9 2. DQM Truth Table V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n−1 = state at 1 clock cycle before n. Notes : • MB81ES171625; DQM0 and DQM1 control DQ7 to DQ0 and DQ15 to DQ8, respectively. • MB81ES173225; DQM0, DQM1, DQM2 and DQM3 control DQ7 to DQ0, DQ15 to DQ8, DQ23 to DQ16, and DQ31 to DQ24, respectively. • All commands assume no CSUS command on previous rising edge of clock. • All commands are assumed to be valid state transition. • All inputs are latched on the rising edge of clock. • TBST, BME and DSE should be held Low. • S16 should be held VIH, and S32 should be held VIL. 3. CKE Truth Table V = Valid, L = Logic Low, H = Logic High, X = either L or H, n = state at current clock cycle, n−1 = state at 1 clock cycle before n. *1 : CSUS command requires that at least one bank is active. Refer to “sSTATE DIAGRAM”. *2 : REF and SELF commands should be issued only after all banks have been precharged (PRE or PALL command). Refer to “sSTATE DIAGRAM”. *3 : SELF and PD commands should be issued only after the last read data have been appeared on DQ. *4 : CKE should be held High during tREFC. Notes: • TBST,BME and DSE should be held Low. • S16 should be held VIH, and S32 should be held VIL. • All commands assume no CSUS command on previous rising edge of clock. • All commands assumed to be valid state transition. • All inputs are latched on the rising edge of clock. Function Command CKE DQM n-1 n Data Input/Output Enable ENBL H X L Data Input/Output Disable MASK H X H Current State Function Com- mand CKE XCS XRAS XCAS XWE BA A10/ AP A12, A11, A9 to A0 n-1 n Bank Active Clock Suspend Mode Entry *1 CSUS H L X X X X X X X Any (Except Idle) Clock Suspend Continue *1 LL X X X X X X X Clock Suspend Clock Suspend Mode Exit LH X X X X X X X Idle Auto-refresh Command *2 REF H H L L L H X X X Idle Self-refresh Entry *2, *3 SELF H L L L L H X X X Self Refresh Self-refresh Exit *4 SELFX LH L H H H X X X LH H X X X X X X Idle Power Down Entry *3 PD HL L H H H X X X HL H X X X X X X Power Down Power Down Exit LH L H H H X X X LH H X X X X X X |
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