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IC61LV12816-12K Datasheet(PDF) 11 Page - Integrated Circuit Solution Inc

Part # IC61LV12816-12K
Description  128K x 16 Hight Speed SRAM with 3.3V
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Manufacturer  ICSI [Integrated Circuit Solution Inc]
Direct Link  http://www.icsi.com.tw
Logo ICSI - Integrated Circuit Solution Inc

IC61LV12816-12K Datasheet(HTML) 11 Page - Integrated Circuit Solution Inc

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IC61LV12816
Integrated Circuit Solution, Inc.
11
AHSR024-0B
04/23/2004
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WRITE CYCLE NO. 4 (1,3)(LB, UB Controlled, Back-to-Back Write)
DATA UNDEFINED
t WC
ADDRESS 1
ADDRESS 2
t WC
HIGH-Z
t PWB
WORD 1
LOW
WORD 2
t HD
t SA
t HZWE
ADDRESS
CE
UB, LB
WE
DOUT
DIN
OE
DATAIN
VALID
t LZWE
t SD
t PWB
DATAIN
VALID
t SD
t HD
t SA
t HA
t HA
Notes:
1. The internal Write time is defined by the overlap of CE = LOW, UB and/or LB = LOW, and WE = LOW. All signals must be
in valid states to initiate a Write, but any can be deasserted to terminate the Write. The
tSA, tHA, t SD, and tHD timing is
referenced to the rising or falling edge of the signal that terminates the Write.
2. Tested with OE HIGH for a minimum of 4 ns before WE = LOW to place the I/O in a HIGH-Z state.
3. WE may be held LOW across many address cycles and the LB, UB pins can be used to control the Write function.


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