TMS28F400BZT, TMS28F400BZB

524288 BY 8-BIT/262144 BY 16-BIT

BOOT-BLOCK FLASH MEMORIES

SMJS400E – JUNE 1994 – REVISED JANUARY 1998

3

POST OFFICE BOX 1443

functional block diagram

Counter

Address

Address

Latch

Control

Reduction

Power-

X Decoder

Y Decoder

Y Gating / Sensing

Block

Main

128K-Byte

Block

Main

128K-Byte

Block

Main

128K-Byte

Block

Main

96K-Byte

Block

Parameter

8K-Byte

Block

Parameter

8K-Byte

Block

Boot

16K-Byte

I/O Logic

Program/

Voltage

Switch

Erase

Machine

State

Write

Machine

State

Command

Data

Comparator

Register

Data

Input

Buffer

Input

Buffer

Register

Status

Register

Identification

Multiplexer

Output

Input Buffer

DQ15/A –1

Output

Buffer

Buffer

Output

DQ8 – DQ15/A –1

DQ0 – DQ7

A0 –

A17

BYTE

E

W

G

RP

VPP

Input

Buffer

18

8

8

8

architecture

The TMS28F400BZx uses a blocked architecture to allow independent erasure of selected memory blocks. The

block to be erased is selected by using any valid address within that block.

block memory maps

The TMS28F400BZx is available with the block architecture mapped in either of two configurations: the boot

block located at the top or at the bottom of the memory array, as required by different microprocessors. The

TMS28F400BZB (bottom boot block ) is mapped with the 16K-byte boot block located at the low-order address

range (00000h to 01FFFh). The TMS28F400BZT (top boot block ) is inverted with respect to the

TMS28F400BZB (bottom boot block) since the boot block is located at the high-order address range (3E000h

to 3FFFFh). Both of these address ranges are for word-wide mode. Figure 1 and Figure 2 show the memory

maps for these configurations.