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SPT5230 Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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SPT5230 Datasheet(HTML) 3 Page - Fairchild Semiconductor |
3 / 7 page 3 5/1/00 SPT5230 INTERFACE CONSIDERATIONS Figure 4 shows a typical interface circuit of the SPT5230 in normal circuit operation. SUPPLY AND GROUND CONSIDERATIONS Fairchild suggests that all power supply pins (AVDD) be tied together and decoupled using a 0.1 µF ceramic capacitor in parallel with a 10 µF tantalum capacitor. EXTERNAL REFERENCE VOLTAGE (VREF1) A +3 V ( ±10%) voltage reference should be externally gener- ated for the VREF1 pin using the simple voltage divider shown in figure 4. Connect a 0.1 µF bypass capacitor between VREF1 and AVSS as close to the pin as possible. EXTERNAL REFERENCE VOLTAGE (VREF2) VREF2 needs to be externally connected to AVDD through a 1.2 k Ω (5%) resistor. Connect a 0.1 µF bypass capacitor between VREF2 and AVSS as close to the pin as possible. CONTROL VOLTAGE DECOUPLING (VCS1) This is a decoupling pin for the control voltage internal circuitry. An external 0.1 µF capacitor should be connected between VCS1 and AVSS as close to the pin as possible. FULL-SCALE ADJUST CONTROL (VCS2) VCS2 is an external control voltage input that controls the peak-to-peak full scale output voltage. This is the only exter- nal voltage that has direct control over the SPT5230 output voltage. The voltage output swings between AVDD (+5 V) and a value controlled by VCS2. Assuming that an output load resistor of 75 Ω is connected between the output and AVDD, figure 2 shows what the output voltage will be for the digital inputs all equal to logic 0, as VCS2 is varied from 2 V to 4 V. Figure 3 shows the peak-to-peak output voltage versus VCS2 and table I shows an example in which VCS2 is equal to 2.1 V. CURRENT OUTPUTS Each red, green and blue current output should have a load resistor connected to AVDD. The resistors are typically 75 Ω and should be kept in the 72 Ω to 85 Ω range. The outputs should drive a high impedance load such as a voltage follower. OUTPUT LEVEL SHIFTING CIRCUIT The SPT5230 voltage output will swing from +3.0 V to +4.99 V for VCS2 = 2.1 V as shown in table I. If level shifting of the output is desired, Fairchild recommends use of the circuit shown in figure 5. The desired –FS voltage is fed into the collector of the emitter to achieve the desired level shift. (Note the phase inversion that will occur due to the common emitter.) Choose any appropriate video op amp with ad- equate power supply head room. Table I – Binary Codes 1 LSB = 1.953 mV, VCS2 ≈ 2.1 V Digital Input Analog Step A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Out (V) (MSB) (LSB) 0 0000000000 3.000000 1 0000000001 3.001953 2 0000000010 3.003906 3 0000000011 3.005859 . . . . . . . . . 1022 1111111110 4.996094 1023 1111111111 4.998047 |
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