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High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rev. 1.2
Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. .
P 8
NOTES:
1. /WE is high in read Cycle.
2. Device is continuously selected when /CE = VIL.
3. Address valid prior to or coincident with CE transition low.
4. /OE = VIL.
5. Transition is measured ±500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE
(1,2,4)
READ CYCLE
(1,3,4)
READ CYCLE
(1,4)