 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADSP-21262SKBC-200 Datasheet(PDF) 8 Page - Analog Devices |
|
||||||||||||||||||||||||||||||
ADSP-21262SKBC-200 Datasheet(HTML) 8 Page - Analog Devices |
|
|
8 / 44 page  Rev. A | Page 8 of 44 | May 2004 ADSP-21262 Serial ports operate in four modes: • Standard DSP serial mode • Multichannel (TDM) mode •I2S mode • Left-justified sample pair mode Left-justified sample pair mode is a mode where in each frame sync cycle two samples of data are transmitted/received—one sample on the high segment of the frame sync, the other on the low segment of the frame sync. Programs have control over var- ious attributes of this mode. Each of the serial ports supports the left-justified sample pair and I2S protocols (I2S is an industry standard interface com- monly used by audio codecs, ADCs and DACs), with two data pins, allowing four left-justified Sample Pair or I2S channels (using two stereo devices) per serial port, with a maximum of up to 24 audio channels. The serial ports permit little-endian or big-endian transmission formats and word lengths selectable from 3 bits to 32 bits. For the left-justified sample pair and I2S modes, data-word lengths are selectable between 8 bits and 32 bits. Serial ports offer selectable synchronization and transmit modes as well as optional µ-law or A-law companding selection on a per channel basis. Serial port clocks and frame syncs can be internally or externally generated. Serial Peripheral (Compatible) Interface Serial Peripheral Interface (SPI) is an industry standard syn- chronous serial link, enabling the ADSP-21262 SPI-compatible port to communicate with other SPI-compatible devices. SPI is an interface consisting of two data pins, one device select pin, and one clock pin. It is a full-duplex synchronous serial inter- face, supporting both master and slave modes. The SPI port can operate in a multimaster environment by interfacing with up to four other SPI-compatible devices, either acting as a master or slave device. The ADSP-21262 SPI compatible peripheral imple- mentation also features programmable baud rates up to 37.5 MHz, clock phases, and polarities. The ADSP-21262 SPI compatible port uses open drain drivers to support a multimas- ter configuration and to avoid data contention. Parallel Port The Parallel Port provides interfaces to SRAM and peripheral devices. The multiplexed address and data pins (AD15-0) can access 8-bit devices with up to 24 bits of address, or 16-bit devices with up to 16 bits of address. In either mode, 8- or 16- bit, the maximum data transfer rate is one-third the core clock speed. As an example, for a clock rate of 200 MHz, this is equiv- alent to 66M Bytes/sec. DMA transfers are used to move data to and from internal memory. Access to the core is also facilitated through the paral- lel port register read/write functions. The RD, WR, and ALE (Address Latch Enable) pins are the control pins for the parallel port. Timers The ADSP-21262 has a total of four timers: a core timer able to generate periodic software interrupts and three general-purpose timers that can generate periodic interrupts and be indepen- dently set to operate in one of three modes: • Pulse Waveform Generation mode • Pulse Width Count/Capture mode • External Event Watchdog mode The core timer can be configured to use FLAG3 as a Timer Expired output signal, and each general-purpose timer has one bidirectional pin and four registers that implement its mode of operation: a 6-bit configuration register, a 32-bit count register, a 32-bit period register, and a 32-bit pulse width register. A sin- gle control and status register enables or disables all three general-purpose timers independently. ROM Based Security The ADSP-21262 has a ROM security feature that provides hardware support for securing user software code by preventing unauthorized reading from the internal code when enabled. When using this feature, the DSP does not boot-load any exter- nal code, executing exclusively from internal SRAM/ROM. Additionally, the DSP is not freely accessible via the JTAG port. Instead, a unique 64-bit key, which must be scanned in through the JTAG or Test Access Port will be assigned to each customer. The device will ignore a wrong key. Emulation features and external boot modes are only available after the correct key is scanned. Program Booting The internal memory of the ADSP-21262 boots at system power-up from an 8-bit EPROM via the parallel port, an SPI master, an SPI slave or an internal boot. Booting is determined by the Boot Configuration (BOOTCFG1-0) pins. Selection of the boot source is controlled via the SPI as either a master or slave device, or it can immediately begin executing from ROM. Phase-Locked Loop The ADSP-21262 uses an on-chip Phase-Locked Loop (PLL) to generate the internal clock for the core. On power-up, the CLKCFG1-0 pins are used to select ratios of 16:1, 8:1, and 3:1. After booting, numerous other ratios can be selected via soft- ware control. The ratios are made up of software configurable numerator values from 1 to 32 and software configurable divi- sor values of 1, 2, 4, 8, and 16. Power Supplies The ADSP-21262 has separate power supply connections for the internal (VDDINT), external (VDDEXT), and analog (AVDD/AVSS) power supplies. The internal and analog supplies must meet the 1.2 V requirement. The external supply must meet the 3.3 V requirement. All external supply pins must be connected to the same power supply. Note that the analog supply (AVDD) powers the ADSP-21262’s clock generator PLL. To produce a stable clock, programs should provide an external circuit to filter the power input to |
Similar Part No. - ADSP-21262SKBC-200 |
|
Similar Description - ADSP-21262SKBC-200 |
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
