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CS5335-KS Datasheet(PDF) 10 Page - Cirrus Logic |
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CS5335-KS Datasheet(HTML) 10 Page - Cirrus Logic |
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10 / 20 page  High Pass Filter The operational amplifiers in the input circuitry driving the CS5334/5 may generate a small DC offset into the A/D converter. The CS5334 and CS5335 include a high pass filter after the deci- mator to remove any DC offset which could result in recording a DC level, possibly yielding "clicks" when switching between devices in a multichannel system. The high pass filter can be disabled with the HP DEFEAT pin. The high pass filter works by continuously subtracting a measure of the dc offset from the output of the decimation filter. If the HP DEFEAT pin is taken high during normal operation, the current value of the dc offset register is frozen and this dc offset will continue to be subtracted from the conversion result. This feature makes it possible to perform a system calibration by; 1. removing the signal source (or grounding the input signal) at the input to the subsystem con- taining the CS5334/5, 2. running the CS5334/5 with the HP DEFEAT pin low (high pass filter enabled) until the filter settles (approximately 1 second), and 3. taking the HP DEFEAT pin high, disabling the high pass filter and freezing the stored dc offset. A system calibration performed in this way will eliminate offsets anywhere in the signal path be- tween the calibration point and the CS5334/5. The characteristics of the first-order high pass filter are outlined below for an output sample rate of 48 kHz. This filter response scales line- arly with sample rate. Frequency response: -3 dB @ 0.9 Hz -0.01 dB @ 20 Hz Phase deviation: 2.6 degrees @ 20 Hz Passband ripple: None INPUT LEVEL MONITORING The CS5334 and CS5335 include independent Peak Input Level Monitoring for each channel. The analog-to-digital converter continually moni- tors the peak digital signal for both channels, prior to the digital limiter, and records these val- ues in the Active registers. This information can be transferred to the Output registers by a high to low transition on the Peak Update pin (PU) which will also reset the Active register. The Ac- tive register contains the peak signal level since the previous peak update request. The 8-bit contents of the output registers are available in all interface modes and are present in the data block as shown in Figure 2. The monitoring function can be formatted to indicate either High Resolution Mode or Bar Graph Mode. The monitoring function is determined on power-up by the presence of a 47 kohm pull- down resistor on FRAME. The addition of a 47 kohm pull-down resistor on the FRAME pin sets the monitoring function to the Bar Graph mode. High Resolution Mode Bits P7-P0 indicate the peak input level since the previous peak update (or low transition on the Peak Update pin). If the full scale input level is exceeded (Bit P7 high), bits P5-P0 represent the peak value up to 3 dB above full-scale in 1 dB steps. If the ADC input level is less than full- scale, bits P5-P0 represent the peak value from -60 dB to 0 dB of full scale in 1 dB steps. The PSL outputs are accurate to within 0.25 dB. Bit P6 provides a coarse means of determining an ADC input idle condition. Bit P7 indicates an ADC overflow condition, if the ADC input level is greater than full-scale. CS5334 CS5335 10 DS237PP2 |
Similar Part No. - CS5335-KS |
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